- 16 Feb, 2024 4 commits
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Luca Weiss authored
Add the description for the display panel found on this phone. Unfortunately the LCDB module on PM6150L isn't yet supported upstream so we need to use a dummy regulator-fixed in the meantime. And with this done we can also enable the GPU and set the zap shader firmware path. Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by:
Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20240216-fp4-panel-v3-4-a556e4b79640@fairphone.comSigned-off-by:
Bjorn Andersson <andersson@kernel.org>
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Luca Weiss authored
The GMU won't probe without GPU being enabled, so we can remove the disabled status so we don't have to explicitly enable the GMU in all the devices that enable GPU. Reviewed-by:
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Joe Mason authored
Like the Samsung Galaxy A3/A5, the Grand Prime/Core Prime uses a Richtek RT5033 PMIC as battery fuel gauge, charger, flash LED and for some regulators. For now, only add the fuel gauge/battery device to the device tree, so we can check the remaining battery percentage. The other RT5033 drivers need some more work first before they can be used properly. Signed-off-by:
Joe Mason <buddyjojo06@outlook.com> [Raymond: Move to fortuna-common. Use interrupts-extended] Signed-off-by:
Raymond Hackley <raymondhackley@protonmail.com> Reviewed-by:
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Luca Weiss authored
Add the definition for the interconnect used in the display subsystem. Signed-off-by:
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- 14 Feb, 2024 19 commits
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Walter Broemeling authored
Samsung Galaxy Core Prime and Grand Prime are phones based on MSM8916. They are similar to the other Samsung devices based on MSM8916 with only a few minor differences. This initial commit adds support for: - fortuna3g (SM-G530H) - gprimeltecan (SM-G530W) - grandprimelte (SM-G530FZ) - rossa (SM-G360G) The device trees contain initial support with: - GPIO keys - Regulator haptic - SDHCI (internal and external storage) - USB Device Mode - UART (on USB connector via the SM5502/SM5504 MUIC) - WCNSS (WiFi/BT) - Regulators - QDSP6 audio - Speaker/earpiece/headphones/microphones via digital/analog codec in MSM8916/PM8916 - WWAN Internet via BAM-DMUX There are different variants of Core Prime and Grand Prime, with some differences in accelerometer, NFC and panel. Core Prime and Grand Prime are similar, with some differences in MUIC, panel and touchscreen. The common parts are shared in msm8916-samsung-fortuna-common.dtsi and msm8916-samsung-rossa-common.dtsi to reduce duplication. Signed-off-by:
Walter Broemeling <wallebroem@gmail.com> Signed-off-by:
Stephan Gerhold <stephan@gerhold.net> [Joe: Add audio, buttons and WiFi] Signed-off-by:
Siddharth Manthan <siddharth.manthan@gmail.com> [Raymond: Add modem, fortuna-common.dtsi, grandprimelte and rossa] Signed-off-by:
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Konrad Dybcio authored
Now that the non-legacy form of OPP is supported within the UFS driver, go ahead and switch to it, adding support for more intermediate freq/power states. Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Link: https://lore.kernel.org/r/20240203-topic-8550_ufs_oppv2-v2-1-b0bef2a73e6c@linaro.orgSigned-off-by:
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Krzysztof Kozlowski authored
Each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe hosts. This also corrects PCIe1 and PCIe2 first MSI interrupt. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Tested-by:
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Krzysztof Kozlowski authored
The DTS code coding style expects exactly one space before '{' and around '=' characters. Signed-off-by:Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240208105208.128706-1-krzysztof.kozlowski@linaro.orgSigned-off-by:
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Krzysztof Kozlowski authored
Neither bindings nor UFS phy driver use properties like 'vdda-phy-max-microamp' and 'vdda-pll-max-microamp': sm7125-xiaomi-curtana.dtb: phy@1d87000: 'vdda-phy-max-microamp', 'vdda-pll-max-microamp' do not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by:
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Krzysztof Kozlowski authored
Add sound card to X1E80100-CRD board and update DMIC supply. Works so far: - Audio playback via speakers or audio jack headset, - DMIC0-3 recording. Reviewed-by:
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Krzysztof Kozlowski authored
Correct the TLMM pin configuration and muxing node names used for DMIC2 and DMIC3 (dmic01 -> dmic23). This has no functional impact, but improves code readability and avoids any confusion when reading the DTS. Signed-off-by:
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Krzysztof Kozlowski authored
Correct the TLMM pin configuration and muxing node names used for DMIC2 and DMIC3 (dmic01 -> dmic23). This has no functional impact, but improves code readability and avoids any confusion when reading the DTS. Signed-off-by:
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Krzysztof Kozlowski authored
Correct the TLMM pin configuration and muxing node names used for DMIC2 and DMIC3 (dmic01 -> dmic23). This has no functional impact, but improves code readability and avoids any confusion when reading the DTS. Signed-off-by:
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Krzysztof Kozlowski authored
Correct the TLMM pin configuration and muxing node names used for DMIC2 and DMIC3 (dmic01 -> dmic23). This has no functional impact, but improves code readability and avoids any confusion when reading the DTS. Signed-off-by:
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Krzysztof Kozlowski authored
Correct the TLMM pin configuration and muxing node names used for DMIC2 and DMIC3 (dmic01 -> dmic23). This has no functional impact, but improves code readability and avoids any confusion when reading the DTS. Signed-off-by:
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Mark Hasemeyer authored
The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. Reviewed-by:
Douglas Anderson <dianders@chromium.org> Signed-off-by:
Mark Hasemeyer <markhas@chromium.org> Link: https://lore.kernel.org/r/20240102140734.v4.16.I870e2c3490e7fc27a8f6bc41dba23b3dfacd2d13@changeidSigned-off-by:
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Mark Hasemeyer authored
The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. Reviewed-by:
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Mark Hasemeyer authored
The cros_ec driver currently assumes that cros-ec-spi compatible device nodes are a wakeup-source even though the wakeup-source property is not defined. Some Chromebooks use a separate wake pin, while others overload the interrupt for wake and IO. With the current assumption, spurious wakes can occur on systems that use a separate wake pin. It is planned to update the driver to no longer assume that the EC interrupt pin should be enabled for wake. Add the wakeup-source property to all cros-ec-spi compatible device nodes to signify to the driver that they should still be a valid wakeup source. Reviewed-by:
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Konrad Dybcio authored
The SLPI is powered by the Low Power Island power rails. Fix the incorrect assignment. Fixes: 74588aad ("arm64: dts: qcom: sdm845: add SLPI remoteproc") Signed-off-by:
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Yassine Oudjana authored
These limits were always defined as 0, but that didn't cause any issue since the driver had hardcoded limits. In commit b4e13e1a ("scsi: ufs: qcom: Add multiple frequency support for MAX_CORE_CLK_1US_CYCLES") the hardcoded limits were removed and the driver started reading them from DT, causing UFS to stop working on MSM8996. Add real UniPro clock limits to fix UFS. Signed-off-by:
Yassine Oudjana <y.oudjana@protonmail.com> Fixes: 57fc67ef ("arm64: dts: qcom: msm8996: Add ufs related nodes") Reviewed-by:
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Bjorn Andersson authored
The SC7280 GCC binding describes clocks which, due to the difference in security model, are not accessible on the RB3gen2 - in the same way seen on QCM6490. Mark these clocks as protected, to allow the board to boot. In contrast to the present QCM6490 boards GCC_EDP_CLKREF_EN is left out, as this does not need to be "protected" and is used on the RB3Gen2 board. Reviewed-by:
Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20240209-qcm6490-gcc-protected-clocks-v2-1-11cd5fc13bd0@quicinc.comSigned-off-by:
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Bjorn Andersson authored
sc8280xp-pmics define the two thermal zones "pm8280-1-thermal" and "pm8280-2-thermal", but the related temp-alarm instances are not tied to any adc channels, and as such continuously report the bogus temperature of 37C. After previously defining these adc channels across all boards using sc8280xp-pmics.dtsi, we can now add these references. This does however mean that we have a non-disabled node referencing default-disabled nodes, requiring each board to enable the pmk8280_vadc. Avoid this by marking pmk8280_vadc okay. Signed-off-by:
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Bjorn Andersson authored
The die-temp vadc channels are not defined for the CRD, but describing them directly would directly duplicate the definition from the Lenovo Thinkpad X13s DeviceTree. The sc8280xp-pmics file describes the common configuration of PMK8280, two PMC8280, PMC8280C, and PMR735a. As such, even though these vadc channels makes references across PMICs, it's suitable to define them in the shared file. Do this, and enable the pmk8280 vadc for the CRD. Signed-off-by:
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- 09 Feb, 2024 5 commits
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Dmitry Baryshkov authored
Plug in USB-C related bits and pieces to enable USB role switching and USB-C orientation handling for the Qualcomm RB2 board. Signed-off-by:
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Vladimir Zapolskiy authored
Stop selecting UTMI clock as the USB3 PIPE clock. This setting is incompatible with the USB host working in USB3 (SuperSpeed) mode. While we are at it, also drop the default setting for the port speed. Fixes: 9dd5f6db ("arm64: dts: qcom: sm6115: Add USB SS qmp phy node") Signed-off-by:
Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> [DB: fixed commit message, dropped dr_mode setting] Reviewed-by:
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Dmitry Baryshkov authored
Define VBUS regulator and the Type-C handling block as present on the Quacomm PMI632 PMIC. Reviewed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by:
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Komal Bajaj authored
Min and max voltages for vph_pwr should be same, otherwise rpmh will not probe, so correcting the min and max voltages for vph_pwr. Fixes: 04cf333a ("arm64: dts: qcom: Add base qcs6490-rb3gen2 board dts") Signed-off-by:
Komal Bajaj <quic_kbajaj@quicinc.com> Reviewed-by:
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Komal Bajaj authored
Min and max voltages for vph_pwr should be same, otherwise rpmh will not probe, so correcting the min and max voltages for vph_pwr. Fixes: 9af6a9f3 ("arm64: dts: qcom: Add base qcm6490 idp board dts") Signed-off-by:
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- 07 Feb, 2024 1 commit
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Bjorn Andersson authored
The SC8280XP contains two additional tsens instances, providing among other things thermal measurements for the GPU. Add these and a GPU thermal-zone. Reviewed-by:
Johan Hovold <johan+linaro@kernel.org> Signed-off-by:
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- 06 Feb, 2024 11 commits
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Neil Armstrong authored
Starting from SM8550, the TX ADC input soundwire port is offset by 1, and uses the new SWR_INPUTx input ports, so replace the legacy SWR_ADCx routes for SWR_INPUT0 & SWR_INPUT1 following the correct TX Soundwire port mapping. Add some comments on the routing for clarity. Fixes: b5e25ded ("arm64: dts: qcom: sm8550: add support for the SM8550-HDK board") Signed-off-by:
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Manivannan Sadhasivam authored
QMP PHY used in SM8650 requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from TCSR Fixes: 10e02467 ("arm64: dts: qcom: sm8650: add interconnect dependent device nodes") Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by:
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Manivannan Sadhasivam authored
QMP PHY used in SM8550 requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from TCSR Fixes: 35cf1aaa ("arm64: dts: qcom: sm8550: Add UFS host controller and phy nodes") Reviewed-by:
Can Guo <quic_cang@quicinc.com> Reviewed-by:
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Manivannan Sadhasivam authored
QMP PHY used in SM8350 requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC While at it, let's move 'clocks' property before 'clock-names' to match the style used commonly. Fixes: 59c7cf81 ("arm64: dts: qcom: sm8350: Add UFS nodes") Reviewed-by:
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Manivannan Sadhasivam authored
QMP PHY used in SC8280XP requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC Fixes: 152d1faf ("arm64: dts: qcom: add SC8280XP platform") Signed-off-by:
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Manivannan Sadhasivam authored
QMP PHY used in SC8180X requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC Fixes: 8575f197 ("arm64: dts: qcom: Introduce the SC8180x platform") Reviewed-by:
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Bjorn Andersson authored
Merge clock topic branch that introduces the SC8180X CLK_REF enable clocks.
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Manivannan Sadhasivam authored
QMP PHY used in SM8250 requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC While at it, let's move 'clocks' property before 'clock-names' to match the style used commonly. Fixes: b7e2fba0 ("arm64: dts: qcom: sm8250: Add UFS controller and PHY") Reviewed-by:
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Manivannan Sadhasivam authored
QMP PHY used in SM8150 requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC While at it, let's move 'clocks' property before 'clock-names' to match the style used commonly. Fixes: 3834a2e9 ("arm64: dts: qcom: sm8150: Add ufs nodes") Reviewed-by:
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Manivannan Sadhasivam authored
QMP PHY used in SM6350 requires 3 clocks: * ref - 19.2MHz reference clock from RPMh * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC While at it, let's move 'clocks' property before 'clock-names' to match the style used commonly. Fixes: 5a814af5 ("arm64: dts: qcom: sm6350: Add UFS nodes") Reviewed-by:
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Manivannan Sadhasivam authored
QMP PHY used in SM6125 requires 3 clocks: * ref - 19.2MHz reference clock from RPM * ref_aux - Auxiliary reference clock from GCC * qref - QREF clock from GCC Fixes: f8399e8a ("arm64: dts: qcom: sm6125: Add UFS nodes") Reviewed-by:
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