1. 06 Jan, 2022 2 commits
  2. 27 Dec, 2021 2 commits
    • Dinh Nguyen's avatar
      ARM: dts: socfpga: change qspi to "intel,socfpga-qspi" · 36de991e
      Dinh Nguyen authored
      Because of commit 9cb2ff11 ("spi: cadence-quadspi: Disable Auto-HW polling"),
      which does a write to the CQSPI_REG_WR_COMPLETION_CTRL register
      regardless of any condition. Well, the Cadence QuadSPI controller on
      Intel's SoCFPGA platforms does not implement the
      CQSPI_REG_WR_COMPLETION_CTRL register, thus a write to this register
      results in a crash!
      
      So starting with v5.16, I introduced the patch
      98d948eb ("spi: cadence-quadspi: fix write completion support"),
      which adds the dts compatible "intel,socfpga-qspi" that is specific for
      versions that doesn't have the CQSPI_REG_WR_COMPLETION_CTRL register implemented.
      Signed-off-by: default avatarDinh Nguyen <dinguyen@kernel.org>
      ---
      v3: revert back to "intel,socfpga-qspi"
      v2: use both "cdns,qspi-nor" and "cdns,qspi-nor-0010"
      36de991e
    • Dinh Nguyen's avatar
      dt-bindings: spi: cadence-quadspi: document "intel,socfpga-qspi" · f34e8875
      Dinh Nguyen authored
      The QSPI controller on Intel's SoCFPGA platform does not implement the
      CQSPI_REG_WR_COMPLETION_CTRL register, thus a write to this register
      results in a crash.
      
      Introduce the dts compatible "intel,socfpga-qspi" to differentiate the
      hardware.
      Acked-by: default avatarPratyush Yadav <p.yadav@ti.com>
      Reviewed-by: default avatarRob Herring <robh@kernel.org>
      Signed-off-by: default avatarDinh Nguyen <dinguyen@kernel.org>
      ---
      v3: revert to "intel,socfpga-qspi"
      v2: change binding to "cdns,qspi-nor-0010" to be more generic for other
          platforms
      f34e8875
  3. 26 Dec, 2021 4 commits
  4. 25 Dec, 2021 12 commits
  5. 24 Dec, 2021 3 commits
  6. 23 Dec, 2021 17 commits