- 15 May, 2018 40 commits
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Tony Cheng authored
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Tony Cheng <tony.cheng@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Hersen Wu authored
remove limit YUV422 color depth to 24bits which is workaround for old ASIC Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Reviewed-by:
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Eric Bernstein authored
Also rename otg_blank to blank_pixel_data. Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
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Eric Bernstein authored
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Anthony Koo authored
Check in code was incorrect, and infopacket is only transmitted after update function is called multiple times. Purpose of the function was to check if infopackets are being enabled, and then enable global control. Fix the code to do this. Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Harry Wentland authored
The below commit "drm/atomic: Try to preserve the crtc enabled state in drm_atomic_remove_fb, v2" introduces a slight behavioral change to rmfb. Instead of disabling a crtc when the primary plane is disabled, it now preserves it. Since DC is currently not equipped to handle this we need to fail such a commit, otherwise we might see a corrupted screen. This is based on Shirish's previous approach but avoids adding all planes to the new atomic state which leads to a full update in DC for any commit, and is not what we intend. Theoretically DM should be able to deal with states with fully populated planes, even for simple updates, such as cursor updates. This should still be addressed in the future. Signed-off-by:Michel Dänzer <michel.daenzer@amd.com> Reviewed-by:
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Mikita Lipski authored
Merge amdgpu_dm_display_resume function into dm_resume, as it is not called anywhere else anymore. Initially the call was broken down into 2 functions for cursor corruption issue. Now the issue is not visible, hence the dm_resume will perform dm_display_resume in it. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
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Mikita Lipski authored
Lock irq table when reading a work in queue, unlock to flush the work, lock again till all tasks are cleared Signed-off-by:
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Emily Deng authored
After host os reset gpu reset, need to set flag in_gpu_reset to zero. Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Reviewed-by:
Monk Liu <monk.liu@amd.com> Signed-off-by:
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Emily Deng authored
When put the IB test out of exclusive mode, and do sriov reset, the IB test will randomly fail. As out of exclusive mode it uses kiq to do read and write registers, but as it has world switch, the kiq read and write time will be random, sometimes it will beyond the MAX_KIQ_REG_WAIT and then the read or write register will fail, which will result the IB test fail. Signed-off-by:
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Pixel Ding authored
The current sequence in scheduler thread is: 1. update last sched fence 2. job begin (adding to mirror list) 3. job finish (remove from mirror list) 4. back to 1 Since we update last sched prior to joining mirror list, the jobs in mirror list already pass the last sched fence. TDR just run the jobs in mirror list, so we should not update the last sched fences in TDR. Signed-off-by:
Pixel Ding <Pixel.Ding@amd.com> Reviewed-by:
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Eric Huang authored
Add the powertune table for VEGAM. Signed-off-by:
Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by:
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Eric Huang authored
VEGAM specific changes for smu7: 1. add avfs control. 2. add a smc message defferent as smu7. 3. don't switch mc arb memory timing. 4. update LCAC_MC0/1_CNTL value. Signed-off-by:
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Eric Huang authored
The smumgr handles communication between the driver and the SMU for power management. v2: fix typo (Alex) Signed-off-by:
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Eric Huang authored
Add functionality to fetch gpio table from vbios. Signed-off-by:
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Eric Huang authored
used for calculating memory clocks in powerplay. v2: handle endian swapping of atom data (Alex) Signed-off-by:
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Eric Huang authored
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Eric Huang authored
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Harry Wentland authored
Some eDP displays use the extra link rate table to advertise link rate support. If they do that they don't need to provide link rate through the usual registers. Since we don't currently have support for the extra link rate table default to HBR2 for the display in this. Note that this is a HACK. Ultimately we need to teach DC to use the extra link rate table. Signed-off-by:
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Alex Deucher authored
DC is preferred. Signed-off-by: -
Jerry (Fangzhi) Zuo authored
Add CHIP_VEGAM Signed-off-by:
Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by:
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Jerry (Fangzhi) Zuo authored
Implement device IDs for VEGAM Signed-off-by:
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Leo Liu authored
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Leo Liu <leo.liu@amd.com> Reviewed-by:
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Leo Liu authored
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Leo Liu authored
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Leo Liu authored
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Leo Liu authored
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Leo Liu authored
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Leo Liu authored
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Leo Liu authored
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Leo Liu authored
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Leo Liu authored
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Leo Liu authored
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Leo Liu authored
v2: use proper register rather than hardcoding. Signed-off-by:
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Leo Liu authored
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Leo Liu authored
Directly loaded by VBIOS Signed-off-by:
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Leo Liu authored
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Leo Liu authored
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Leo Liu authored
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Leo Liu authored
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