- 19 Dec, 2023 11 commits
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Samson Tam authored
[Why] On resume from S3, while DMUB is inactive, DMUB queue and execute calls will not work. Skip reporting errors in these scenarios [How] Add new return code during DMUB queue and execute calls when DMUB is in S3 state. Skip logging errors in these scenarios Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
Wayne Lin <wayne.lin@amd.com> Signed-off-by:
Samson Tam <samson.tam@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Xiaogang Chen authored
SVM uses hmm page walk to valid buffer before map to gpu vm. After have partial migration/mapping do validation on same vm range as migration/map do instead of whole svm range that can be very large. This change is expected to improve svm code performance. Signed-off-by:
Xiaogang Chen <xiaogang.chen@amd.com> Reviewed-by:
Philip Yang <philip.yang@amd.com> Signed-off-by:
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Mario Limonciello authored
It is reported that on a Topaz dGPU the kernel emits: amdgpu: can't get the mac of 5 This is because there is no definition for max levels of VDDGFX declared for SMU71 or SMU7. The correct definition is VDDC so use this. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3049Reviewed-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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Mario Limonciello authored
`/` wasn't meant to be in the Dragon Range line Reviewed-by:
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Mario Limonciello authored
These have been announced so add them to the table. Link: https://www.amd.com/en/product/13971Reviewed-by:
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Josip Pavic authored
[Why] This variable currently overflows after about 71 minutes. This doesn't cause any known functional issues but it does make debugging more difficult. [How] Make it a 64-bit variable. Reviewed-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
Josip Pavic <josip.pavic@amd.com> Tested-by:
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Wayne Lin authored
[Why & how] Refactor dc_is_dmub_outbox_supported() a bit and add case for dcn35 to register dmub outbox notification irq to handle usb4 relevant hpd event. Reviewed-by:
Roman Li <roman.li@amd.com> Reviewed-by:
Jun Lei <jun.lei@amd.com> Signed-off-by:
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Hamza Mahfooz authored
There have recently been changes that break backwards compatibility, that were introduced into DMUB firmware (for DCN32x) concerning FPO and SubVP. So, since those are just power optimization features, we can just disable them unless the user is using a new enough version of DMUB firmware. Cc: stable@vger.kernel.org Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2870 Fixes: ed6e2782 ("drm/amd/display: For cursor P-State allow for SubVP") Reported-by:
Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com> Closes: https://lore.kernel.org/r/CABXGCsNRb0QbF2pKLJMDhVOKxyGD6-E+8p-4QO6FOWa6zp22_A@mail.gmail.com/Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Mario Limonciello authored
Some issues have been raised that appear to be tied to PSR-SU. To allow users to confirm they're tied to PSR-SU without turning off PSR entirely introduce a new debug mask: amdgpu.dcdebugmask=0x200 Reviewed-by:
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Johnson Chen authored
[why] Allow devs to check raw clk register values by dumping them on the log [how] Add clk register dump implementation Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Acked-by:
Johnson Chen <johnson.chen@amd.com> Tested-by:
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Aric Cyr authored
[why] There is only a single call to dc_post_update_surfaces_to_stream so there is no need to have two flags to control it. Unifying this to a single flag allows dc_stream_adjust_vmin_vmax to skip actual programming when there is no change required. [how] Remove wm_optimze_required flag and set only optimize_required in its place. Then in dc_stream_adjust_vmin_vmax, check that the stream timing range matches the requested one and skip programming if they are equal. Reviewed-by:
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- 15 Dec, 2023 8 commits
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Alvin Lee authored
[Description] Revert commit fec05adc ("drm/amd/display: Use channel_width = 2 for vram table 3.0") Because the issue is being fixed from VBIOS side. Reviewed-by:
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Muhammad Ahmed authored
[why & how] Add config to make HPO PG handled in dmubfw ips entry/exit Reviewed-by:
Muhammad Ahmed <ahmed.ahmed@amd.com> Tested-by:
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Samson Tam authored
[Why] On resume from S3, may get apply_idle_optimizations call while DMUB is inactive which will just time out. [How] Set and track power state in dmub_srv and check power state before sending commands to DMUB. Add interface in both dmub_srv and dc_dmub_srv Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
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Li Ma authored
There is a repeated define of smu v14_0_0 driver if version, so delete one in driver if header. Signed-off-by:
Li Ma <li.ma@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by:
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James Zhu authored
Only schedule when hmm_range_fault returns error. Signed-off-by:
James Zhu <James.Zhu@amd.com> Acked-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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James Zhu authored
When application tries to allocate all system memory and cause memory to swap out. Needs more time for hmm_range_fault to validate the remaining page for allocation. To be safe, increase timeout value to 1 second for 64MB range. Signed-off-by:
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Philip Yang authored
On gfx943 APU there is no VRAM and page migration, queue CWSR area, svm range with always mapped flag, is not mapped to GPU correctly. This works fine if retry fault on CWSR area can be recovered, but could cause deadlock if there is another retry fault recover waiting for CWSR to finish. Fix this by mapping svm range with always mapped flag to GPU with ACCESS attribute if XNACK ON. There is side effect, because all GPUs have ACCESS attribute by default on new svm range with XNACK on, the CWSR area will be mapped to all GPUs after this change. This side effect will be fixed with Thunk change to set CWSR svm range with ACCESS_IN_PLACE attribute on the GPU that user queue is created. Signed-off-by:
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Jonathan Kim authored
Fix up on mes process context flush to prevent non-mes devices from spamming error messages or running into undefined behaviour during process termination. Fixes: bd33bb14 ("drm/amdkfd: fix mes set shader debugger process management") Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Reviewed-by:
Eric Huang <jinhuieric.huang@amd.com> Signed-off-by:
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- 14 Dec, 2023 20 commits
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Melissa Wen authored
warning: expecting prototype for drm_crtc_additional_color_mgmt(). Prototype was for dm_crtc_additional_color_mgmt() instead Reported-by:
kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202312141801.o9eBCxt9-lkp@intel.com/Signed-off-by:
Melissa Wen <mwen@igalia.com> Signed-off-by:
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Alex Deucher authored
It takes the plane state rather than the crtc state. Fixes: aba8b76b ("drm/amd/display: add plane shaper LUT support") Reported-by:
Stephen Rothwell <sfr@canb.auug.org.au> Reviewed-by:
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Zhipeng Lu authored
The amdgpu_free_extended_power_table is called in every error-handling paths of amdgpu_parse_extended_power_table. However, after the following call chain of returning: amdgpu_parse_extended_power_table |-> kv_dpm_init / si_dpm_init (the only two caller of amdgpu_parse_extended_power_table) |-> kv_dpm_sw_init / si_dpm_sw_init (the only caller of kv_dpm_init / si_dpm_init, accordingly) |-> kv_dpm_fini / si_dpm_fini (goto dpm_failed in xx_dpm_sw_init) |-> amdgpu_free_extended_power_table As above, the amdgpu_free_extended_power_table is called twice in this returning chain and thus a double-free is triggered. Similarily, the last kfree in amdgpu_parse_extended_power_table also cause a double free with amdgpu_free_extended_power_table in kv_dpm_fini. Fixes: 84176663 ("drm/amd/pm: create a new holder for those APIs used only by legacy ASICs(si/kv)") Signed-off-by:Zhipeng Lu <alexious@zju.edu.cn> Signed-off-by:
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Zhipeng Lu authored
When radeon_bo_create and radeon_vm_clear_bo fail, the vm->page_tables allocated before need to be freed. However, neither radeon_vm_init itself nor its caller have done such deallocation. Fixes: 6d2f2944 ("drm/radeon: use normal BOs for the page tables v4") Signed-off-by:
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Zhipeng Lu authored
When ps allocated by kzalloc equals to NULL, kv_parse_power_table frees adev->pm.dpm.ps that allocated before. However, after the control flow goes through the following call chains: kv_parse_power_table |-> kv_dpm_init |-> kv_dpm_sw_init |-> kv_dpm_fini The adev->pm.dpm.ps is used in the for loop of kv_dpm_fini after its first free in kv_parse_power_table and causes a use-after-free bug. Fixes: a2e73f56 ("drm/amdgpu: Add support for CIK parts") Signed-off-by: -
Zhipeng Lu authored
When the allocation of adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries fails, amdgpu_free_extended_power_table is called to free some fields of adev. However, when the control flow returns to si_dpm_sw_init, it goes to label dpm_failed and calls si_dpm_fini, which calls amdgpu_free_extended_power_table again and free those fields again. Thus a double-free is triggered. Fixes: 841686df ("drm/amdgpu: add SI DPM support (v4)") Signed-off-by:
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Yang Li authored
./drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c:1418:2-3: Unneeded semicolon Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=7743Signed-off-by:
Yang Li <yang.lee@linux.alibaba.com> Signed-off-by:
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Alex Deucher authored
Should be -EOPNOTSUPP. Fixes: 5104fdf5 ("drm/amdgpu: Fix a null pointer access when the smc_rreg pointer is NULL") Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Joshua Ashton authored
Create drm_color_ctm_3x4 to support 3x4-dimension plane CTM matrix and convert DRM CTM to DC CSC float matrix. v3: - rename ctm2 to ctm_3x4 (Harry) Reviewed-by:
Joshua Ashton <joshua@froggi.es> Signed-off-by:
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Melissa Wen authored
Map the plane CTM driver-specific property to DC plane, instead of DC stream. The remaining steps to program DPP block are already implemented on DC shared-code. v3: - fix comment about plane and CRTC CTMs priorities (Harry) Reviewed-by:
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Kenneth Feng authored
add power save mode workload for smu 13.0.10, so that in compute mode, pmfw will add margin since some applications requres higher margin. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Signed-off-by:
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Peyton Lee authored
enable vpe dpm Signed-off-by:
Peyton Lee <peytolee@amd.com> Reviewed-by:
Lang Yu <lang.yu@amd.com> Signed-off-by:
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Melissa Wen authored
Plane CTM for pre-blending color space conversion. Only enable driver-specific plane CTM property on drivers that support both pre- and post-blending gamut remap matrix, i.e., DCN3+ family. Otherwise it conflits with DRM CRTC CTM property. Reviewed-by:
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Joshua Ashton authored
When commiting planes, we copy color mgmt resources to the stream state. Do the same for shaper and 3D LUTs. Reviewed-by:
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Peyton Lee authored
pm supports return vpe clock table and soc clock table Signed-off-by:
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Wang, Beyond authored
Issue: during evict or validate happened on amdgpu_bo, the 'from' and 'to' is always same in ftrace event of amdgpu_bo_move where calling the 'trace_amdgpu_bo_move', the comment says move_notify is called before move happens, but actually it is called after move happens, here the new_mem is same as bo->resource Fix: move trace_amdgpu_bo_move from move_notify to amdgpu_bo_move Signed-off-by:
Wang, Beyond <Wang.Beyond@amd.com> Reviewed-by:
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Joshua Ashton authored
Need to funnel the color caps through to these functions so it can check that the hardware is capable. v2: - remove redundant color caps assignment on plane degamma map (Harry) - pass color caps to degamma params v3: - remove unused color_caps parameter from set_color_properties (Harry) Reviewed-by:
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Joshua Ashton authored
Map plane blend properties to DPP blend gamma. Plane blend is a post-3D LUT curve that linearizes color space for blending. It may be defined by a user-blob LUT and/or predefined transfer function. As hardcoded curve (ROM) is not supported on blend gamma, we use AMD color module to fill parameters when setting non-linear TF with empty LUT. v2: - rename DRM TFs to AMDGPU TFs Reviewed-by:
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Joshua Ashton authored
Unlike degamma, blend gamma doesn't support hardcoded curve (predefined/ROM), but we can use AMD color module to fill blend gamma parameters when we have non-linear plane gamma TF without plane gamma LUT. The regular degamma path doesn't hit this. Reviewed-by:
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Melissa Wen authored
Wire up DC 3D LUT to DM plane color management (pre-blending). On AMD display HW, 3D LUT comes after a shaper curve and we always have to program a shaper curve to delinearize or normalize the color space before applying a 3D LUT (since we have a reduced number of LUT entries). In this version, the default values of 3D LUT for size and bit_depth are 17x17x17 and 12-bit, but we already provide here a more generic mechanisms to program other supported values (9x9x9 size and 10-bit). v2: - started with plane 3D LUT instead of CRTC 3D LUT support v4: - lut3d_size is the max dimension size instead of # of entries Reviewed-by:
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- 13 Dec, 2023 1 commit
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Christian König authored
This can only happen when there is a reference counting bug. v2: fix typo Signed-off-by:
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