1. 19 Apr, 2023 3 commits
    • Song Shuai's avatar
      riscv: Kconfig: enable SCHED_MC kconfig · 8bf7b3b6
      Song Shuai authored
      RISC-V now builds the sched domain based on the simple possible map.
      
      Enable SCHED_MC to make the building based on cpu_coregroup_mask()
      which also takes care of the NUMA and cores with LLC.
      Signed-off-by: default avatarSong Shuai <suagrfillet@gmail.com>
      Acked-by: default avatarConor Dooley <conor.dooley@microchip.com>
      Link: https://lore.kernel.org/r/20230310110336.970985-1-suagrfillet@gmail.comSigned-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
      8bf7b3b6
    • Song Shuai's avatar
      riscv: export cpu/freq invariant to scheduler · c4b52d8b
      Song Shuai authored
      RISC-V now manages CPU topology using arch_topology which provides
      CPU capacity and frequency related interfaces to access the cpu/freq
      invariant in possible heterogeneous or DVFS-enabled platforms.
      
      Here adds topology.h file to export the arch_topology interfaces for
      replacing the scheduler's constant-based cpu/freq invariant accounting.
      Signed-off-by: default avatarSong Shuai <suagrfillet@gmail.com>
      Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
      Reviewed-by: default avatarLey Foon Tan <lftan@kernel.org>
      Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
      Link: https://lore.kernel.org/r/20230323123924.3032174-1-suagrfillet@gmail.com
      [Palmer: Fix the whitespace issues.]
      Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
      c4b52d8b
    • Palmer Dabbelt's avatar
      Merge patch series "RISC-V Hardware Probing User Interface" · eb04e72b
      Palmer Dabbelt authored
      Evan Green <evan@rivosinc.com> says:
      
      There's been a bunch of off-list discussions about this, including at
      Plumbers.  The original plan was to do something involving providing an
      ISA string to userspace, but ISA strings just aren't sufficient for a
      stable ABI any more: in order to parse an ISA string users need the
      version of the specifications that the string is written to, the version
      of each extension (sometimes at a finer granularity than the RISC-V
      releases/versions encode), and the expected use case for the ISA string
      (ie, is it a U-mode or M-mode string).  That's a lot of complexity to
      try and keep ABI compatible and it's probably going to continue to grow,
      as even if there's no more complexity in the specifications we'll have
      to deal with the various ISA string parsing oddities that end up all
      over userspace.
      
      Instead this patch set takes a very different approach and provides a set
      of key/value pairs that encode various bits about the system.  The big
      advantage here is that we can clearly define what these mean so we can
      ensure ABI stability, but it also allows us to encode information that's
      unlikely to ever appear in an ISA string (see the misaligned access
      performance, for example).  The resulting interface looks a lot like
      what arm64 and x86 do, and will hopefully fit well into something like
      ACPI in the future.
      
      The actual user interface is a syscall, with a vDSO function in front of
      it. The vDSO function can answer some queries without a syscall at all,
      and falls back to the syscall for cases it doesn't have answers to.
      Currently we prepopulate it with an array of answers for all keys and
      a CPU set of "all CPUs". This can be adjusted as necessary to provide
      fast answers to the most common queries.
      
      An example series in glibc exposing this syscall and using it in an
      ifunc selector for memcpy can be found at [1].
      
      I was asked about the performance delta between this and something like
      sysfs. I created a small test program and ran it on a Nezha D1
      Allwinner board. Doing each operation 100000 times and dividing, these
      operations take the following amount of time:
       - open()+read()+close() of /sys/kernel/cpu_byteorder: 3.8us
       - access("/sys/kernel/cpu_byteorder", R_OK): 1.3us
       - riscv_hwprobe() vDSO and syscall: .0094us
       - riscv_hwprobe() vDSO with no syscall: 0.0091us
      
      These numbers get farther apart if we query multiple keys, as sysfs will
      scale linearly with the number of keys, where the dedicated syscall
      stays the same. To frame these numbers, I also did a tight
      fork/exec/wait loop, which I measured as 4.8ms. So doing 4
      open/read/close operations is a delta of about 0.3%, versus a single vDSO
      call is a delta of essentially zero.
      
      [1] https://patchwork.ozlabs.org/project/glibc/list/?series=343050
      
      * b4-shazam-merge:
        RISC-V: Add hwprobe vDSO function and data
        selftests: Test the new RISC-V hwprobe interface
        RISC-V: hwprobe: Support probing of misaligned access performance
        RISC-V: hwprobe: Add support for RISCV_HWPROBE_BASE_BEHAVIOR_IMA
        RISC-V: Add a syscall for HW probing
        RISC-V: Move struct riscv_cpuinfo to new header
      
      Link: https://lore.kernel.org/r/20230407231103.2622178-1-evan@rivosinc.comSigned-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
      eb04e72b
  2. 18 Apr, 2023 6 commits
  3. 11 Apr, 2023 2 commits
  4. 29 Mar, 2023 4 commits
  5. 27 Mar, 2023 3 commits
  6. 24 Mar, 2023 1 commit
    • Palmer Dabbelt's avatar
      Merge patch series "riscv: Add GENERIC_ENTRY support" · e45d6a52
      Palmer Dabbelt authored
      guoren@kernel.org <guoren@kernel.org> says:
      
      From: Guo Ren <guoren@linux.alibaba.com>
      
      The patches convert riscv to use the generic entry infrastructure from
      kernel/entry/*. Some optimization for entry.S with new .macro and merge
      ret_from_kernel_thread into ret_from_fork.
      
      * b4-shazam-merge:
        riscv: entry: Consolidate general regs saving/restoring
        riscv: entry: Consolidate ret_from_kernel_thread into ret_from_fork
        riscv: entry: Remove extra level wrappers of trace_hardirqs_{on,off}
        riscv: entry: Convert to generic entry
        riscv: entry: Add noinstr to prevent instrumentation inserted
        riscv: ptrace: Remove duplicate operation
      
      Link: https://lore.kernel.org/r/20230222033021.983168-1-guoren@kernel.orgSigned-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
      e45d6a52
  7. 23 Mar, 2023 6 commits
  8. 15 Mar, 2023 15 commits