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  1. 15 Sep, 2018 2 commits
    • Jacopo Mondi's avatar
      drm: rcar-du: Improve non-DPLL clock selection · 8c74c456
      Jacopo Mondi authored 
      DU channels not equipped with a DPLL use an SoC internal (provided by
the CPG) or external clock source combined with a DU internal divider to
generate the desired output dot clock frequency.

The current clock selection procedure does not fully exploit the ability
of external clock sources to generate the exact dot clock frequency by
themselves, but relies instead on tuning the internal DU clock divider
only, resulting in a less precise clock generation process.

When possible, and desirable, ask the external clock source for the
exact output dot clock frequency, and select the clock source that
produces the frequency closest to the desired output dot clock.

This patch specifically targets platforms (like Salvator-X[S] and ULCBs)
where the DU's input dotclock.in is generated by the versaclock VC5
clock source, which is capable of generating the exact rate the DU needs
as pixel clock output.

This patch fixes higher resolution modes which requires an high pixel
clock output currently not working on non-HDMI DU channel (such as
1920x1080@60Hz on the VGA output).

Fixes: 1b30dbde ("drm: rcar-du: Add support for external pixel clock")
Signed-off-by: default avatarJacopo Mondi <jacopo@jmondi.org>
[Factor out code to a helper function]
Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: default avatarJacopo Mondi <jacopo+renesas@jmondi.org>
      8c74c456
    • Laurent Pinchart's avatar
      drm: rcar-du: Rework clock configuration based on hardware limits · 7281e6c6
      Laurent Pinchart authored 
      The DU channels that have a display PLL (DPLL) can only use external
clock sources, and don't have an internal clock divider (with the
exception of H3 ES1.x where the post-divider is present and needs to be
used as a workaround for a DPLL silicon issue).

Rework the clock configuration to take this into account, avoiding
selection of non-existing clock sources or usage of a missing
post-divider.
Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: default avatarJacopo Mondi <jacopo+renesas@jmondi.org>
      7281e6c6
  3. 14 Sep, 2018 10 commits
  5. 13 Sep, 2018 3 commits
  7. 12 Sep, 2018 14 commits
  9. 11 Sep, 2018 11 commits
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