- 14 Jun, 2024 40 commits
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Yang Wang authored
refine psp firmware loading Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Yunxiang Li authored
We need to take the reset domain lock before talking to MES. While in this case we can take the lock inside the mes helper. We can't do so for most other mes helpers since they are used during reset. So for consistency sake we add the lock here. Signed-off-by:
Yunxiang Li <Yunxiang.Li@amd.com> Reviewed-by:
Felix Kuehling <felix.kuehling@amd.com> Signed-off-by:
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Yang Wang authored
v1: refine mes firmware loading v2: use dev_info instead of DRM_INFO Signed-off-by:
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Mukul Joshi authored
Add missing locking at a few places when calling MES APIs to ensure exclusive access to MES queue. Signed-off-by:
Mukul Joshi <mukul.joshi@amd.com> Reviewed-by:
Kent Russell <kent.russell@amd.com> Signed-off-by:
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Mario Limonciello authored
Currently, amdgpu will always set up the brightness at 100% when it loads. However this is jarring when the BIOS has it previously programmed to a much lower value. The ACPI ATIF method includes two members for "ac_level" and "dc_level". These represent the default values that should be used if the system is brought up in AC and DC respectively. Use these values to set up the default brightness when the backlight device is registered. v2: squash in ACPI fix Reviewed-by:
Leo Li <sunpeng.li@amd.com> Acked-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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David (Ming Qiang) Wu authored
Similar to commit 813e7d4c where some kernel log messages are dropped. With this commit, more log messages in older version of VCN/JPEG code are dropped. Acked-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
David (Ming Qiang) Wu <David.Wu3@amd.com> Signed-off-by:
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Ivan Lipski authored
Revert "drm/amd/display: Add NULL check for 'afb' before dereferencing in amdgpu_dm_plane_handle_cursor_update" [WHY] This patch is a dupplicate implementation of 14bcf29b, which we are reverting due to a regression with kms_plane_cursor IGT tests. This reverts commit 38e6f715. Reviewed-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Tested-by:
George Zhang <George.zhang@amd.com> Signed-off-by:
Ivan Lipski <ivlipski@amd.com> Signed-off-by:
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Ivan Lipski authored
[WHY] This commit introduced a regression with kms_plane_cursor IGT tests, causing AMD Asics to fail these tests. This reverts commit ce66ffd9. Reviewed-by:
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Yang Wang authored
refine gpu_info firmware loading Signed-off-by:
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Hamza Mahfooz authored
We can't read/write to DCN registers while in IPS. Since, that can cause the system to hang. So, before proceeding with the access in that scenario, force the system out of IPS. Cc: stable@vger.kernel.org # 6.6+ Reviewed-by:
Roman Li <roman.li@amd.com> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Yang Wang authored
v1: Adding formatting string feature to improve function flexibility. v2: modify macro name to ADMGPU_UCODE_MAX_NAME. Signed-off-by:
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Bob Zhou authored
To fix potential overflowed constant warning reported by Coverity, modify the variables to uint32_t. Signed-off-by:
Bob Zhou <bob.zhou@amd.com> Acked-by:
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Yunxiang Li authored
We need to take the reset domain lock before flush hdp. We can't put the lock inside amdgpu_device_flush_hdp itself because it is used during reset where we already take the write side lock. Signed-off-by:
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Yunxiang Li authored
Which method is used to flush tlb does not depend on whether a reset is in progress or not. We should skip flush altogether if the GPU will get reset. So put both path under reset_domain read lock. Signed-off-by:
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Yunxiang Li authored
Here since we are in reset and takes the reset_domain write side lock already. We can't use the flush tlb helper which tries to take the read side. Signed-off-by:
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Yunxiang Li authored
When amdgpu_gart_invalidate_tlb helper is introduced this part was left out of the conversion. Avoid the code duplication here. Signed-off-by:
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Yunxiang Li authored
At this point the gart is not set up, there's no point to invalidate tlb here and it could even be harmful. Signed-off-by:
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Yunxiang Li authored
is_hws_hang and is_resetting serves pretty much the same purpose and they all duplicates the work of the reset_domain lock, just check that directly instead. This also eliminate a few bugs listed below and get rid of dqm->ops.pre_reset. kfd_hws_hang did not need to avoid scheduling another reset. If the on-going reset decided to skip GPU reset we have a bad time, otherwise the extra reset will get cancelled anyway. remove_queue_mes forgot to check is_resetting flag compared to the pre-MES path unmap_queue_cpsch, so it did not block hw access during reset correctly. Signed-off-by:
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Yunxiang Li authored
We send back the ready to reset message before we stop anything. This is wrong. Move it to when we are actually ready for the FLR to happen. In the current state since we take tens of seconds to stop everything, it is very likely that host would give up waiting and reset the GPU before we send ready, so it would be the same as before. But this gets rid of the hack with reset_domain locking and also let us tell how slow ready to reset actually is from the host. The ready to reset speed can be improved later. Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Signed-off-by:
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Yunxiang Li authored
Accessing registers via host is missing the check for skip_hw_access and the lockdep check that comes with it. Signed-off-by:
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Eric Huang authored
To fullfill the reset event description. Suggested-by:
Lijo Lazar <Lijo.Lazar@amd.com> Signed-off-by:
Eric Huang <jinhuieric.huang@amd.com> Reviewed-by:
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Eric Huang authored
amdgpu_job_ring may return NULL, which causes kernel NULL pointer error, using another way to print ring name instead of ring->name. Suggested-by:
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Aric Cyr authored
This version brings the following changes: - Add sequential ONO sequencing for DCN35 - Add new GPINT command definitions - reduce ODM slice count to initial new dc state only when needed - Enable copying of bounding box data from VBIOS DMUB - Guard reading 3DLUT registers for dcn32/dcn35 Reviewed-by:
Zaeem Mohamed <zaeem.mohamed@amd.com> Acked-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Sung Joon Kim authored
[why] There are other factors that determine the number of DSC slices. The slices should not be determined in DML but retrieve the value calculated from driver. [how] Update the logic to determine DSC slice. Make DSCDelay per display pipe. Reviewed-by:
Jun Lei <jun.lei@amd.com> Acked-by:
Sung Joon Kim <sungjoon.kim@amd.com> Tested-by:
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Alex Hung authored
Two additional virtual links are created and thus increasing size for dc->links by two. Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
Alex Hung <alex.hung@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why] 3DLUT is not part of the DPP on DCN32/DCN35 ASIC and these registers now exist in MCM state. [How] Add guards when reading DPP state based on whether the register has a valid offset. Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by:
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Dillon Varone authored
- Ensure SubVP stream settings match ODM policy - Fix MALL size calculations when DCC is enabled - Fail if any stream fails DRR policy check Reviewed-by:
Chaitanya Dhere <chaitanya.dhere@amd.com> Acked-by:
Dillon Varone <dillon.varone@amd.com> Tested-by:
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Alvin Lee authored
[Description] In newer DCN's the programming of SYMCLK_FE_SRC_SEL depends on the value of DIG_FE_SOURCE_SELECT. If DIG_FE_SOURCE_SELECT is not already programmed at the time of PHY / DIG enable then the FW sequence will program an incorrect SYMCLK source. Ensure that we program DIG_FE_SOURCE_SELECT for all DIO scenarios (DVI in this particular case) before going through the PHY / DIG enable sequence. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
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Jesse Zhang authored
Since the range of the varibable i is 0 - 3. So execution cannot reach this statement: default. Signed-off-by:
Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by:
Tim Huang <Tim.Huang@amd.com> Signed-off-by:
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Jesse Zhang authored
Since the range of align is 0~7, the expression is: align = (attr >> 3) & 7. In the case of ATOM_ARG_IMM, the code cannot reach the default case. So there is no need for "break". Signed-off-by:
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ChunTao Tso authored
Add functions to defer updating of coasting vtotal after source refresh rate update. Reviewed-by:
Robin Chen <robin.chen@amd.com> Acked-by:
ChunTao Tso <chuntao.tso@amd.com> Tested-by:
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Srinivasan Shanmugam authored
drm/amd/display: Add NULL check for 'afb' before dereferencing in amdgpu_dm_plane_handle_cursor_update This commit adds a null check for the 'afb' variable in the amdgpu_dm_plane_handle_cursor_update function. Previously, 'afb' was assumed to be null, but was used later in the code without a null check. This could potentially lead to a null pointer dereference. Fixes the below: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.c:1298 amdgpu_dm_plane_handle_cursor_update() error: we previously assumed 'afb' could be null (see line 1252) Cc: Tom Chung <chiahsuan.chung@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Roman Li <roman.li@amd.com> Cc: Hersen Wu <hersenxs.wu@amd.com> Cc: Alex Hung <alex.hung@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Srinivasan Shanmugam authored
This commit adds a null check for the 'afb' variable in the amdgpu_dm_update_cursor function. Previously, 'afb' was assumed to be null at line 8388, but was used later in the code without a null check. This could potentially lead to a null pointer dereference. Fixes the below: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:8433 amdgpu_dm_update_cursor() error: we previously assumed 'afb' could be null (see line 8388) drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c 8379 static void amdgpu_dm_update_cursor(struct drm_plane *plane, 8380 struct drm_plane_state *old_plane_state, 8381 struct dc_stream_update *update) 8382 { 8383 struct amdgpu_device *adev = drm_to_adev(plane->dev); 8384 struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); 8385 struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; ^^^^^ 8386 struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; 8387 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 8388 uint64_t address = afb ? afb->address : 0; ^^^^^ Checks for NULL 8389 struct dc_cursor_position position = {0}; 8390 struct dc_cursor_attributes attributes; 8391 int ret; 8392 8393 if (!plane->state->fb && !old_plane_state->fb) 8394 return; 8395 8396 drm_dbg_atomic(plane->dev, "crtc_id=%d with size %d to %d\n", 8397 amdgpu_crtc->crtc_id, plane->state->crtc_w, 8398 plane->state->crtc_h); 8399 8400 ret = amdgpu_dm_plane_get_cursor_position(plane, crtc, &position); 8401 if (ret) 8402 return; 8403 8404 if (!position.enable) { 8405 /* turn off cursor */ 8406 if (crtc_state && crtc_state->stream) { 8407 dc_stream_set_cursor_position(crtc_state->stream, 8408 &position); 8409 update->cursor_position = &crtc_state->stream->cursor_position; 8410 } 8411 return; 8412 } 8413 8414 amdgpu_crtc->cursor_width = plane->state->crtc_w; 8415 amdgpu_crtc->cursor_height = plane->state->crtc_h; 8416 8417 memset(&attributes, 0, sizeof(attributes)); 8418 attributes.address.high_part = upper_32_bits(address); 8419 attributes.address.low_part = lower_32_bits(address); 8420 attributes.width = plane->state->crtc_w; 8421 attributes.height = plane->state->crtc_h; 8422 attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; 8423 attributes.rotation_angle = 0; 8424 attributes.attribute_flags.value = 0; 8425 8426 /* Enable cursor degamma ROM on DCN3+ for implicit sRGB degamma in DRM 8427 * legacy gamma setup. 8428 */ 8429 if (crtc_state->cm_is_degamma_srgb && 8430 adev->dm.dc->caps.color.dpp.gamma_corr) 8431 attributes.attribute_flags.bits.ENABLE_CURSOR_DEGAMMA = 1; 8432 --> 8433 attributes.pitch = afb->base.pitches[0] / afb->base.format->cpp[0]; ^^^^^ ^^^^^ Unchecked dereferences 8434 8435 if (crtc_state->stream) { 8436 if (!dc_stream_set_cursor_attributes(crtc_state->stream, 8437 &attributes)) 8438 DRM_ERROR("DC failed to set cursor attributes\n"); 8439 8440 update->cursor_attributes = &crtc_state->stream->cursor_attributes; 8441 8442 if (!dc_stream_set_cursor_position(crtc_state->stream, 8443 &position)) 8444 DRM_ERROR("DC failed to set cursor position\n"); 8445 8446 update->cursor_position = &crtc_state->stream->cursor_position; 8447 } 8448 } Fixes: 66eba12a ("drm/amd/display: Do cursor programming with rest of pipe") Reported-by:Dan Carpenter <dan.carpenter@linaro.org> Cc: Tom Chung <chiahsuan.chung@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Roman Li <roman.li@amd.com> Cc: Hersen Wu <hersenxs.wu@amd.com> Cc: Alex Hung <alex.hung@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Lewis Huang authored
[Why] For some panel, it cannot handle pseudo vblank set by otg resync when leave psr [How] The monitor patch will keep otg_on during enter IPS1. And then we don't need to do otg resync when wake up. Reviewed-by:
Duncan Ma <duncan.ma@amd.com> Acked-by:
Lewis Huang <lewis.huang@amd.com> Tested-by:
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Chiawen Huang authored
[How&Why] Once IPS active, all the DCN resources are not be allowed to access. It needs to a function for 3rd party to on/off IPS. Reviewed-by:
Chiawen Huang <chiawen.huang@amd.com> Tested-by:
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Dillon Varone authored
[WHY&HOW] Add 5ms timeout to trigger recovery and force allow P-State in DMUB. Reviewed-by:
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Dillon Varone authored
[WHY&HOW] UCLK and FCLK are updated together, so an FCLK update can also cause UCLK update to SMU. When this happens, the UCLK provided should be max if switching is unsupported. Reviewed-by:
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Wayne Lin authored
[Why] enc10->base.features.flags.bits.DP_IS_USB_C will be overwritten if we set it before initializing enc10->base.features [How] Determine DP_IS_USB_C after enc10->base.features is initialized. Besides, bp_cap_info.DP_IS_USB_C will never be set in get_connector_speed_cap_info(). Remove the redudant code. Reviewed-by:
Wayne Lin <wayne.lin@amd.com> Tested-by:
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Yihan Zhu authored
[WHY] OPPs couldn't disconnect from the ODM that cause the double buffer pending not being latched due to missing VUPDATE. [HOW] Moving memory blanking before OTG turn off to make sure double buffer latched correctly. Reviewed-by:
Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Acked-by:
Yihan Zhu <yihan.zhu@amd.com> Tested-by:
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Alex Deucher authored
This mirrors what the driver does for older DCN generations. Should fix: [ 26.924055] BUG: sleeping function called from invalid context at include/linux/sched/mm.h:306 [ 26.924060] in_atomic(): 1, irqs_disabled(): 0, non_block: 0, pid: 1022, name: modprobe [ 26.924063] preempt_count: 2, expected: 0 [ 26.924064] RCU nest depth: 0, expected: 0 [ 26.924066] Preemption disabled at: [ 26.924067] [<ffffffffc089e5e0>] dc_fpu_begin+0x30/0xd0 [amdgpu] [ 26.924322] CPU: 9 PID: 1022 Comm: modprobe Not tainted 6.8.0+ #20 [ 26.924325] Hardware name: System manufacturer System Product Name/CROSSHAIR VI HERO, BIOS 6302 10/23/2018 [ 26.924326] Call Trace: [ 26.924327] <TASK> [ 26.924329] dump_stack_lvl+0x37/0x50 [ 26.924333] ? dc_fpu_begin+0x30/0xd0 [amdgpu] [ 26.924589] dump_stack+0x10/0x20 [ 26.924592] __might_resched+0x16a/0x1c0 [ 26.924596] __might_sleep+0x42/0x70 [ 26.924598] __kmalloc_node_track_caller+0x2ad/0x4b0 [ 26.924601] ? dm_helpers_allocate_gpu_mem+0x12/0x20 [amdgpu] [ 26.924855] ? dcn401_update_bw_bounding_box+0x2a/0xf0 [amdgpu] [ 26.925122] kmemdup+0x20/0x50 [ 26.925124] ? kernel_fpu_begin_mask+0x6b/0xe0 [ 26.925127] ? kmemdup+0x20/0x50 [ 26.925129] dcn401_update_bw_bounding_box+0x2a/0xf0 [amdgpu] [ 26.925393] dc_create+0x311/0x670 [amdgpu] [ 26.925649] amdgpu_dm_init+0x2aa/0x1fa0 [amdgpu] [ 26.925903] ? irq_work_queue+0x38/0x50 [ 26.925907] ? vprintk_emit+0x1e7/0x270 [ 26.925910] ? dev_printk_emit+0x83/0xb0 [ 26.925914] ? amdgpu_device_rreg+0x17/0x20 [amdgpu] [ 26.926133] dm_hw_init+0x14/0x30 [amdgpu] v2: drop extra memcpy Fixes: 669d6b07 ("drm/amd/display: avoid large on-stack structures") Reviewed-by:
Arnd Bergmann <arnd@arndb.de> Suggested-by:
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