- 15 Jun, 2023 14 commits
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Chen-Yu Tsai authored
This adds clocks, dynamic power coefficients, and OPP tables for the CPU cores, so that everything required at the SoC level for CPU freqency and voltage scaling is available. Signed-off-by:
Chen-Yu Tsai <wenst@chromium.org> Reviewed-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230609072906.2784594-3-wenst@chromium.orgSigned-off-by:
Matthias Brugger <matthias.bgg@gmail.com>
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Chen-Yu Tsai authored
Add a device node for the CCI (cache coherent interconnect) and an OPP table for it. The OPP table was taken from the downstream ChromeOS kernel. Signed-off-by:
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Daniel Golle authored
Add pwm-fan and cooling-maps to BananaPi-R3 devicetree. Signed-off-by:
Daniel Golle <daniel@makrotopia.org> Signed-off-by:
Frank Wunderlich <frank-w@public-files.de> Reviewed-by:
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Daniel Golle authored
Add thermal-zones to mt7986 devicetree. Signed-off-by:
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Daniel Golle authored
Add thermal related nodes to mt7986 devicetree. Signed-off-by:
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Nícolas F. R. A. Prado authored
The capacity-dmips-mhz parameter was miscalculated: this SoC runs the first (Cortex-A55) cluster at a maximum of 2000MHz and the second (Cortex-A76) cluster at a maximum of 2200MHz. In order to calculate the right capacity-dmips-mhz, the following test was performed: 1. CPUFREQ governor was set to 'performance' on both clusters 2. Ran dhrystone with 500000000 iterations for 10 times on each cluster 3. Calculated the mean result for each cluster 4. Calculated DMIPS/MHz: dmips_mhz = dmips_per_second / cpu_mhz 5. Scaled results to 1024: result_c0 = dmips_mhz_c0 / dmips_mhz_c1 * 1024 The mean results for this SoC are: Cluster 0 (LITTLE): 12016411 Dhry/s Cluster 1 (BIG): 31702034 Dhry/s The calculated scaled results are: Cluster 0: 426.953226899238 (rounded to 427) Cluster 1: 1024 Fixes: 48489980 ("arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile") Signed-off-by:
Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by:
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Nícolas F. R. A. Prado authored
In the series "Adjust the dma-ranges for MTK IOMMU", the mtk-iommu driver was adapted to separate the iova range based on the larb used, and a dma-ranges property was added to the soc node in the devicetree of the affected SoCs allowing the whole 16GB iova range to be used. Except that for mt8192, there was no patch adding dma-ranges. Add the missing dma-ranges property to the soc node like was done for mt8195 and mt8186. This fixes the usage of the vcodec, which would otherwise trigger iommu faults. Signed-off-by:
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Hsin-Yi Wang authored
The upstream SCP firmware path is /lib/firmware/mediatek/mt8183/scp.img Signed-off-by:
Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by:
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Yunfei Dong authored
Add video decoder node to mt8195 device tree. Signed-off-by:
Yunfei Dong <yunfei.dong@mediatek.com> Signed-off-by:
Allen-KH Cheng <allen-kh.cheng@mediatek.com> Reviewed-by:
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Allen-KH Cheng authored
Add video-codec lat and core nodes for mt8192 SoC. Signed-off-by:
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Allen-KH Cheng authored
Add the cpufreq nodes for MT8192 SoC. Signed-off-by:
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Icenowy Zheng authored
Currently a specific panel number is used in the Elm DTSI, which is corresponded to a 12" panel. However, according to the official Chrome OS devices document, Elm refers to Acer Chromebook R13, which, as the name specifies, uses a 13.3" panel, which comes with EDID information. As the kernel currently prioritizes the hardcoded timing parameters matched with the panel number compatible, a wrong timing will be applied to the 13.3" panel on Acer Chromebook R13, which leads to blank display. Because the Elm DTSI is shared with Hana board, and Hana corresponds to multiple devices from 11" to 14", a certain panel model number shouldn't be present, and driving the panel according to its EDID information is necessary. Signed-off-by:
Icenowy Zheng <uwu@icenowy.me> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20230526100801.16310-1-uwu@icenowy.meSigned-off-by:
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Frank Wunderlich authored
To store uncompressed bl2 more space is required than partition is actually defined. There is currently no known usage of this reserved partition. Openwrt uses same partition layout. We added same change to u-boot with commit d7bb1099 [1]. [1] https://source.denx.de/u-boot/u-boot/-/commit/d7bb109900c1ca754a0198b9afb50e3161ffc21e Cc: stable@vger.kernel.org Fixes: 8e01fb15 ("arm64: dts: mt7986: add Bananapi R3") Signed-off-by:
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Pin-yen Lin authored
Add "regulator-boot-on" to "panel_fixed_3v3" to save time on powering the regulator during boot. Also add "off-on-delay-us" to the node to make sure the regulator never violates the panel timing requirements. Signed-off-by:
Pin-yen Lin <treapking@chromium.org> Reviewed-by:
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- 29 May, 2023 26 commits
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Frank Wunderlich authored
Leds for Wifi are low-active, so add property to devicetree. Signed-off-by:
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Frank Wunderlich authored
Add pwm node and pinctrl to BananaPi R3 devicetree. Signed-off-by:
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Daniel Golle authored
This adds pwm node to mt7986. Signed-off-by:
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AngeloGioacchino Del Regno authored
The chassis-type string identifies the form-factor of the system: add this property to all device trees of devices for which the form factor is known. Signed-off-by:
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Krzysztof Kozlowski authored
As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like: mt7622-rfb1.dtb: l2-cache: 'cache-unified' is a required property Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230421223157.115367-1-krzysztof.kozlowski@linaro.orgSigned-off-by:
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Douglas Anderson authored
Firmware shipped on mt8195 Chromebooks is affected by the GICR save/restore issue as described by the patch ("dt-bindings: interrupt-controller: arm,gic-v3: Add quirk for Mediatek SoCs w/ broken FW"). Add the quirk property. Fixes: 5eb2e303 ("arm64: dts: mediatek: Introduce MT8195 Cherry platform's Tomato") Reviewed-by:Julius Werner <jwerner@chromium.org> Signed-off-by:
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Douglas Anderson authored
Firmware shipped on mt8192 Chromebooks is affected by the GICR save/restore issue as described by the patch ("dt-bindings: interrupt-controller: arm,gic-v3: Add quirk for Mediatek SoCs w/ broken FW"). Add the quirk property. Fixes: 331fae2f ("arm64: dts: mediatek: Introduce MT8192-based Asurada board family") Reviewed-by: -
Douglas Anderson authored
Firmware shipped on mt8183 Chromebooks is affected by the GICR save/restore issue as described by the patch ("dt-bindings: interrupt-controller: arm,gic-v3: Add quirk for Mediatek SoCs w/ broken FW"). Add the quirk property. Fixes: cd894e27 ("arm64: dts: mt8183: Add krane-sku176 board") Reviewed-by: -
AngeloGioacchino Del Regno authored
On the Cherry platform, a MT7621 WiFi+Bluetooth combo is connected over PCI-Express (for WiFi) and USB (for BT): enable the PCIe ports to enable enumerating this chip. Signed-off-by:
Alexandre Mergnat <amergnat@baylibre.com> Link: https://lore.kernel.org/r/20230424112523.1436926-5-angelogioacchino.delregno@collabora.comSigned-off-by:
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AngeloGioacchino Del Regno authored
Assign aliases for the primary and secondary dp-intf IP to properly and reliably enable DisplayPort functionality. Signed-off-by:
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Chen-Yu Tsai authored
Hayato's Realtek WiFi/BT module has it's Bluetooth function wired to UART1. Add and enable the relevant device nodes for it. Signed-off-by:
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Daniel Golle authored
Since commit ba751e28 ("net: dsa: mt7530: add interrupt support") the mt7530 driver can act as an interrupt controller. Wire up irq line of the MT7531 switch on the BananaPi BPi-R64 board, so the status of the PHYs of the five 1000Base-T ports doesn't need to be polled any more. Signed-off-by:
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Daniel Golle authored
The SPI-NOR node in the device tree of the BananaPi R64 has most likely been copied from the reference board's device tree even though the R64 comes with an SPI-NAND chip rather than SPI-NOR. Setup the Serial NAND Flash Interface (SNFI) controller, enable hardware BCH error detection and correction engine and add the SPI-NAND chip including basic partitions, Signed-off-by:
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AngeloGioacchino Del Regno authored
Configure and enable the MMC0/1/2 controllers, used for the eMMC chip, MicroSD card slot and SDIO (WiFi) respectively. Signed-off-by:
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AngeloGioacchino Del Regno authored
This smartphone uses the Helio X10 standard MT6331+MT6332 combo PMICs: include the mt6331 devicetree and add the required interrupt. Note that despite there being two interrupts, one for MT6331 and one for MT6332, in configurations using the companion PMIC, the interrupt of the latter fires for both events on MT6331 and for ones on MT6332, while the interrupt for the main PMIC fires only for events of the main PMIC. Signed-off-by:
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AngeloGioacchino Del Regno authored
MT6331 is the primary PMIC for the MediaTek Helio X10 MT6795 smartphone platforms: add a devicetree describing its regulators, Real Time Clock and PMIC-keys. Signed-off-by:
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AngeloGioacchino Del Regno authored
Add the pwrap node: this is used to communicate with the PMIC(s). Signed-off-by:
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AngeloGioacchino Del Regno authored
Add nodes for the multimedia IOMMU and its LARBs: this includes all but the MJC LARB, which cannot currently be used and will be added later. Signed-off-by:
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AngeloGioacchino Del Regno authored
Add the MultiMedia System node, providing clocks for the multimedia hardware blocks and their IOMMU/SMIs. Signed-off-by:
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AngeloGioacchino Del Regno authored
In preparation for adding multimedia blocks, add the CMDQ/GCE mailbox. Signed-off-by:
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Balsam CHIHI authored
Add AP Domain thermal zones for the mt8195 and specify the targeted temperature thresholds. Signed-off-by:
Balsam CHIHI <bchihi@baylibre.com> Link: https://lore.kernel.org/r/20230405100907.53740-1-bchihi@baylibre.comSigned-off-by:
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Allen-KH Cheng authored
Add display nodes and the GCE (Global Command Engine) properties to the display nodes in order to enable the usage of the CMDQ (Command Queue), which is required for operating the display. Signed-off-by:
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Allen-KH Cheng authored
Add the Global Command Engine (GCE) node for MT8186 SoC Signed-off-by:
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Allen-KH Cheng authored
Add ADSP node for MT8186 SoC. Signed-off-by:
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Allen-KH Cheng authored
Add SPMI node for MT8186 SoC. Signed-off-by:
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Allen-KH Cheng authored
Add MTU3 nodes for MT8186 SoC. Signed-off-by:
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