- 01 Sep, 2021 4 commits
-
-
Stephen Boyd authored
- Support the SD/OE pin on IDT VersaClock 5 and 6 clock generators * clk-nvidia: clk: tegra: fix old-style declaration clk: tegra: Remove CLK_IS_CRITICAL flag from fuse clock soc/tegra: fuse: Enable fuse clock on suspend for Tegra124 soc/tegra: fuse: Add runtime PM support soc/tegra: fuse: Clear fuse->clk on driver probe failure soc/tegra: pmc: Prevent racing with cpuilde driver soc/tegra: bpmp: Remove unused including <linux/version.h> * clk-rockchip: clk: rockchip: make rk3308 ddrphy4x clock critical clk: rockchip: drop GRF dependency for rk3328/rk3036 pll types dt-bindings: clk: Convert rockchip,rk3399-cru to DT schema clk: rockchip: Add support for hclk_sfc on rk3036 clk: rockchip: rk3036: fix up the sclk_sfc parent error clk: rockchip: add dt-binding clkid for hclk_sfc on rk3036 * clk-at91: clk: at91: clk-generated: Limit the requested rate to our range * clk-vc5: clk: vc5: Add properties for configuring SD/OE behavior clk: vc5: Use dev_err_probe dt-bindings: clk: vc5: Add properties for configuring the SD/OE pin
-
Stephen Boyd authored
- Add power of two flag to fractional divider clk type * clk-frac-divider: clk: fractional-divider: Document the arithmetics used behind the code clk: fractional-divider: Introduce POWER_OF_TWO_PS flag clk: fractional-divider: Hide clk_fractional_divider_ops from wide audience clk: fractional-divider: Export approximation algorithm to the CCF users
-
Stephen Boyd authored
- Migrate some clk drivers to clk_divider_ops.determine_rate * clk-renesas: clk: renesas: Make CLK_R9A06G032 invisible clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2 dt-bindings: clock: r9a07g044-cpg: Add entry for P0_DIV2 core clock clk: renesas: r9a07g044: Add clock and reset entries for ADC clk: renesas: r9a07g044: Add clock and reset entries for CANFD clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch] clk: renesas: r9a07g044: Add GPIO clock and reset entries clk: renesas: r9a07g044: Add SSIF-2 clock and reset entries clk: renesas: r9a07g044: Add USB clocks/resets clk: renesas: r9a07g044: Add DMAC clocks/resets clk: renesas: r9a07g044: Add I2C clocks/resets clk: renesas: r8a779a0: Add the DSI clocks clk: renesas: r8a779a0: Add the DU clock clk: renesas: rzg2: Rename i2c-dvfs to iic-pmic clk: renesas: rzg2l: Fix off-by-one check in rzg2l_cpg_clk_src_twocell_get() clk: renesas: rzg2l: Avoid mixing error pointers and NULL clk: renesas: rzg2l: Fix a double free on error clk: renesas: rzg2l: Fix return value and unused assignment clk: renesas: rzg2l: Remove unneeded semicolon * clk-cleanup: clk: palmas: Add a missing SPDX license header clk: Align provider-specific CLK_* bit definitions * clk-determine-divider: clk: stm32mp1: Switch to clk_divider.determine_rate clk: stm32h7: Switch to clk_divider.determine_rate clk: stm32f4: Switch to clk_divider.determine_rate clk: bcm2835: Switch to clk_divider.determine_rate clk: divider: Implement and wire up .determine_rate by default
-
Stephen Boyd authored
- Support video, gpu, display clks on qcom sc7280 SoCs - GCC clks on qcom MSM8953, SM4250/6115, and SM6350 SoCs - Multimedia clks (MMCC) on qcom MSM8994/MSM8992 - Migrate to clk_parent_data in gcc-sdm660 - RPMh clks on qcom SM6350 SoCs - Support for Mediatek MT8192 SoCs * clk-qcom: (38 commits) clk: qcom: Add SM6350 GCC driver dt-bindings: clock: Add SM6350 GCC clock bindings clk: qcom: rpmh: Add support for RPMH clocks on SM6350 dt-bindings: clock: Add RPMHCC bindings for SM6350 clk: qcom: adjust selects for SM_VIDEOCC_8150 and SM_VIDEOCC_8250 clk: qcom: Add Global Clock controller (GCC) driver for SM6115 dt-bindings: clk: qcom: gcc-sm6115: Document SM6115 GCC clk: qcom: mmcc-msm8994: Add MSM8992 support clk: qcom: Add msm8994 MMCC driver dt-bindings: clock: Add support for MSM8992/4 MMCC clk: qcom: Add Global Clock Controller driver for MSM8953 dt-bindings: clock: add Qualcomm MSM8953 GCC driver bindings clk: qcom: gcc-sdm660: Replace usage of parent_names clk: qcom: gcc-sdm660: Move parent tables after PLLs clk: qcom: use devm_pm_runtime_enable and devm_pm_clk_create PM: runtime: add devm_pm_clk_create helper PM: runtime: add devm_pm_runtime_enable helper clk: qcom: a53-pll: Add MSM8939 a53pll support dt-bindings: clock: Update qcom,a53pll bindings for MSM8939 support clk: qcom: a53pll/mux: Use unique clock name ... * clk-socfpga: clk: socfpga: agilex: add the bypass register for s2f_usr0 clock clk: socfpga: agilex: fix up s2f_user0_clk representation clk: socfpga: agilex: fix the parents of the psi_ref_clk * clk-mediatek: (22 commits) clk: mediatek: make COMMON_CLK_MT8167* depend on COMMON_CLK_MT8167 clk: mediatek: Add MT8192 vencsys clock support clk: mediatek: Add MT8192 vdecsys clock support clk: mediatek: Add MT8192 scp adsp clock support clk: mediatek: Add MT8192 msdc clock support clk: mediatek: Add MT8192 mmsys clock support clk: mediatek: Add MT8192 mfgcfg clock support clk: mediatek: Add MT8192 mdpsys clock support clk: mediatek: Add MT8192 ipesys clock support clk: mediatek: Add MT8192 imp i2c wrapper clock support clk: mediatek: Add MT8192 imgsys clock support clk: mediatek: Add MT8192 camsys clock support clk: mediatek: Add MT8192 audio clock support clk: mediatek: Add MT8192 basic clocks support clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providers clk: mediatek: Add configurable enable control to mtk_pll_data clk: mediatek: Fix asymmetrical PLL enable and disable control clk: mediatek: Get regmap without syscon compatible check clk: mediatek: Add dt-bindings of MT8192 clocks dt-bindings: ARM: Mediatek: Add audsys document binding for MT8192 ... * clk-lmk: clk: lmk04832: drop redundant fallthrough statements * clk-x86: clk: x86: Rename clk-lpt to more specific clk-lpss-atom
-
- 29 Aug, 2021 12 commits
-
-
Arnd Bergmann authored
With extra warnings enabled, gcc complains about a slightly odd prototype: drivers/clk/tegra/clk-dfll.c:1380:1: error: 'inline' is not at beginning of declaration [-Werror=old-style-declaration] 1380 | static void inline dfll_debug_init(struct tegra_dfll *td) { } Move the 'inline' keyword to the start of the line. Signed-off-by:Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20210322215047.1062540-1-arnd@kernel.orgAcked-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
-
Konrad Dybcio authored
This adds Global Clock controller (GCC) driver for SM6350 SoC Acked-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210820203624.232268-3-konrad.dybcio@somainline.orgSigned-off-by:
-
Sean Anderson authored
The SD/OE pin may be configured to enable output when high or low, and to shutdown the device when high. This behavior is controller by the SH and SP bits of the Primary Source and Shutdown Register (and to a lesser extent the OS and OE bits). By default, both bits are 0 (unless set by OTP memory), but they may need to be configured differently, depending on the external circuitry controlling the SD/OE pin. Signed-off-by:
Sean Anderson <sean.anderson@seco.com> Link: https://lore.kernel.org/r/20210809223813.3766204-3-sean.anderson@seco.comReviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
-
Sean Anderson authored
Convert uses of dev_err (+ return) to dev_err_probe. Signed-off-by:
Luca Ceresoli <luca@lucaceresoli.net> Link: https://lore.kernel.org/r/20210809223813.3766204-2-sean.anderson@seco.comSigned-off-by:
-
Sean Anderson authored
These properties allow configuring the SD/OE pin as described in the datasheet. Signed-off-by:
Rob Herring <robh@kernel.org> Reviewed-by:
-
Codrin Ciubotariu authored
On clk_generated_determine_rate(), the requested rate could be outside of clk's range. Limit the rate to the clock's range to not return an error. Fixes: df70aeef ("clk: at91: add generated clock driver") Signed-off-by:
Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Link: https://lore.kernel.org/r/20210707131213.3283509-1-codrin.ciubotariu@microchip.comAcked-by:
Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by:
-
Konrad Dybcio authored
Add device tree bindings for global clock controller on SM6350 SoC. Signed-off-by:
-
Konrad Dybcio authored
Add support for RPMH clocks on SM6350 SoCs. Reviewed-by:
-
Konrad Dybcio authored
Add bindings and update documentation for clock rpmh driver on SM6350. Reviewed-by:
-
Lukas Bulwahn authored
Commit 5658e8cf ("clk: qcom: add video clock controller driver for SM8150") and commit 0e94711a ("clk: qcom: add video clock controller driver for SM8250") add config SM_VIDEOCC_8150 and config SM_VIDEOCC_8250, which select the non-existing configs SDM_GCC_8150 and SDM_GCC_8250, respectively. Hence, ./scripts/checkkconfigsymbols.py warns: SDM_GCC_8150 Referencing files: drivers/clk/qcom/Kconfig SDM_GCC_8250 Referencing files: drivers/clk/qcom/Kconfig It is probably just a typo (or naming confusion of using SM_GCC_xxx and SDM_GCC_xxx for various Qualcomm clock drivers) in the config definitions for config SM_VIDEOCC_8150 and SM_VIDEOCC_8250, and intends to select the existing SM_GCC_8150 and SM_GCC_8250, respectively. Adjust the selects to the existing configs. Signed-off-by:
Lukas Bulwahn <lukas.bulwahn@gmail.com> Link: https://lore.kernel.org/r/20210816135930.11810-1-lukas.bulwahn@gmail.comSigned-off-by:
-
Iskren Chernev authored
Add support for the global clock controller found on SM6115 based devices. This should allow most non-multimedia device drivers to probe and control their clocks. Based on CAF implementation. GDSCs ported from downstream DT. Signed-off-by:
Iskren Chernev <iskren.chernev@gmail.com> Link: https://lore.kernel.org/r/20210805161107.1194521-3-iskren.chernev@gmail.comSigned-off-by:
-
Iskren Chernev authored
Add device tree bindings for global clock controller on SM6115 and SM4250 SoCs (pin and software compatible). Signed-off-by:
-
- 26 Aug, 2021 10 commits
-
-
Konrad Dybcio authored
MSM8992 features less clocks & GDSCS and has different freq tables for some of them. Signed-off-by:
-
Konrad Dybcio authored
Add a driver for managing MultiMedia SubSystem clocks on msm8994 and its derivatives. Signed-off-by:
-
Konrad Dybcio authored
Document the multimedia clock controller found on MSM8992/4. Signed-off-by:
-
Vladimir Lypak authored
This driver provides clocks, resets and power domains for MSM8953 and compatible SoCs: APQ8053, SDM450, SDA450, SDM632, SDA632. Signed-off-by:
Vladimir Lypak <junak.pub@gmail.com> Signed-off-by:
Adam Skladowski <a_skl39@protonmail.com> Reviewed-by:
Sireesh Kodali <sireeshkodali@protonmail.com> Link: https://lore.kernel.org/r/IPvVnyRWbHuQFswiFz0W08Kj1dKoH55ddQVyIIPhMJw@cp7-web-043.plabs.chSigned-off-by:
-
Vladimir Lypak authored
Add bindings and compatible to document MSM8953 GCC (Global Clock Controller) driver. Signed-off-by:
-
Bjorn Andersson authored
Using parent_data and parent_hws, instead of parent_names, does protect against some cases of incompletely defined clock trees. While it turns out that the bug being chased this time was totally unrelated, this patch converts the SDM660 GCC driver to avoid such issues. The "xo" fixed_factor clock is unused within the gcc driver, but referenced from the DSI PHY. So it's left in place until the DSI driver is updated. Tested-by:
Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210825204517.1278130-1-bjorn.andersson@linaro.org [sboyd@kernel.org: Reduce diff by moving enum and tables back to original position in previous patch] Signed-off-by:
-
Stephen Boyd authored
In the next patch we're going to change these tables to reference the PLL structures directly. Let's move them here so the diff is easier to read. No functional change in this patch. Signed-off-by: -
Dmitry Baryshkov authored
Use two new helpers instead of pm_runtime_enable() and pm_clk_create(), removing the need for calling pm_runtime_disable and pm_clk_destroy(). Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210731195034.979084-4-dmitry.baryshkov@linaro.orgSigned-off-by:
-
Dmitry Baryshkov authored
A typical code pattern for pm_clk_create() call is to call it in the _probe function and to call pm_clk_destroy() both from _probe error path and from _remove function. For some drivers the whole remove function would consist of the call to pm_remove_disable(). Add helper function to replace this bolierplate piece of code. Calling devm_pm_clk_create() removes the need for calling pm_clk_destroy() both in the probe()'s error path and in the remove() function. Signed-off-by:
Rafael J. Wysocki <rafael@kernel.org> Signed-off-by:
-
Dmitry Baryshkov authored
A typical code pattern for pm_runtime_enable() call is to call it in the _probe function and to call pm_runtime_disable() both from _probe error path and from _remove function. For some drivers the whole remove function would consist of the call to pm_remove_disable(). Add helper function to replace this bolierplate piece of code. Calling devm_pm_runtime_enable() removes the need for calling pm_runtime_disable() both in the probe()'s error path and in the remove() function. Signed-off-by:
-
- 24 Aug, 2021 3 commits
-
-
Stephen Boyd authored
Merge tag 'v5.15-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip Pull Rockchip clk driver updates from Heiko Stuebner: - YAML conversion of rk3399 clock controller binding - Removal of GRF dependency for the rk3328/rk3036 pll types - some clock tree fixes * tag 'v5.15-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: make rk3308 ddrphy4x clock critical clk: rockchip: drop GRF dependency for rk3328/rk3036 pll types dt-bindings: clk: Convert rockchip,rk3399-cru to DT schema clk: rockchip: Add support for hclk_sfc on rk3036 clk: rockchip: rk3036: fix up the sclk_sfc parent error clk: rockchip: add dt-binding clkid for hclk_sfc on rk3036
-
Stephen Boyd authored
Merge tag 'for-5.15-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-nvidia Pull a Tegra clk driver cleanup from Thierry Reding: The FUSE driver has been updated to take manual control of the FUSE clock over suspend/resume cycles, so the CLK_IS_CRITICAL flag can now be dropped. * tag 'for-5.15-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: clk: tegra: Remove CLK_IS_CRITICAL flag from fuse clock soc/tegra: fuse: Enable fuse clock on suspend for Tegra124 soc/tegra: fuse: Add runtime PM support soc/tegra: fuse: Clear fuse->clk on driver probe failure soc/tegra: pmc: Prevent racing with cpuilde driver soc/tegra: bpmp: Remove unused including <linux/version.h>
-
Stephen Boyd authored
Merge tag 'renesas-clk-for-v5.15-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull more Renesas clk driver updates from Geert Uytterhoeven: - Make CLK_R9A06G032 invisible * tag 'renesas-clk-for-v5.15-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: Make CLK_R9A06G032 invisible
-
- 13 Aug, 2021 1 commit
-
-
Geert Uytterhoeven authored
When configuring a kernel including support for Renesas ARM/ARM64 Socs, but excluding support for the RZ/N1D SoC, the user is always asked about the RZ/N1D clock driver. As this driver is already auto-selected when building a kernel including support for the RZ/N1D SoC, there is no need to make the CLK_R9A06G032 symbol visible, unless compile-testing. Align the symbol description with the other symbols. Signed-off-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/4f3d30c730c30546f702715ffc648922a8156703.1628672649.git.geert+renesas@glider.be
-
- 12 Aug, 2021 4 commits
-
-
Andy Shevchenko authored
It appears that some code lines raise the question why they are needed and how they are participated in the calculus of the resulting values. Document this in a form of the top comment in the module file. Reported-by:
Liu Ying <victor.liu@nxp.com> Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20210812170025.67074-4-andriy.shevchenko@linux.intel.com [sboyd@kernel.org: Remove "die" as it isn't relevant] Signed-off-by:
-
Andy Shevchenko authored
The newly introduced POWER_OF_TWO_PS flag, when set, makes the flow to skip the assumption that the caller will use an additional 2^scale prescaler to get the desired clock rate. Reported-by:
-
Andy Shevchenko authored
The providers are all located in drivers/clk/ and hence no need to export the clock operations to wider audience. Hide them by moving to drivers/clk/clk-fractional-divider.h. Signed-off-by:
-
Andy Shevchenko authored
At least one user currently duplicates some functions that are provided by fractional divider module. Let's export approximation algorithm and replace the open-coded variant. As a bonus the exported function will get better documentation in place. Signed-off-by:
Heiko Stuebner <heiko@sntech.de> Acked-by:
-
- 11 Aug, 2021 6 commits
-
-
Dmitry Osipenko authored
FUSE driver now takes care of keeping the clock enabled when necessary. Remove the CLK_IS_CRITICAL flag from the clock. Signed-off-by:
Dmitry Osipenko <digetx@gmail.com> Signed-off-by:
-
Thierry Reding authored
-
Dmitry Osipenko authored
The FUSE clock should be enabled during suspend on Tegra124. Currently clk driver enables it on all SoCs, but FUSE may require a higher core voltage on Tegra30 while enabled. Move the quirk into the FUSE driver and make it specific to Tegra124. Signed-off-by:
-
Dmitry Osipenko authored
The Tegra FUSE belongs to the core power domain and we're going to enable GENPD support for the core domain. Now FUSE device must be resumed using runtime PM API in order to initialize the FUSE power state. Add runtime PM support to the FUSE driver. Signed-off-by:
-
Dmitry Osipenko authored
The fuse->clk must be cleared if FUSE driver fails to probe, otherwise tegra_fuse_readl() will crash. It's unlikely to happen in practice, nevertheless let's correct it for completeness. Signed-off-by:
-
Dmitry Osipenko authored
Both PMC and cpuidle drivers are probed at the same init level and cpuidle depends on the PMC suspend mode. Add new default suspend mode that indicates whether PMC driver has been probed and reset the mode in a case of deferred probe of the PMC driver. Signed-off-by:
-
