- 06 Jul, 2015 7 commits
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Abdiel Janulgue authored
Adds support for enabling the resource streamer on the legacy ringbuffer for HSW and GEN8. Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
Abdiel Janulgue <abdiel.janulgue@linux.intel.com> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Vandana Kannan authored
This patch contains changes based on 2 updates to the spec: Port PLL VCO restriction raised up to 6700. Port PLL now needs DCO amp override enable for all VCO frequencies. v2: Sonika's review comment addressed - dcoampovr_en_h variable not required Based on a discussion with Siva, the following changes have been made. - replace dco_amp var with #define BXT_DCO_AMPLITUDE - set pll10 in a single assignment v3: Move DCO amplitude default value to i915_reg.h. Suggested by Siva. Signed-off-by:
Vandana Kannan <vandana.kannan@intel.com> Reviewed-by: Sonika Jindal <sonika.jindal@intel.com> [v2] [danvet: Spell out BUN since not everyone knows what this means.] Signed-off-by:
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Ville Syrjälä authored
HDMI 12bpc should be working fine now. Let it loose. This reverts commit 5e3daaca. v2: Rebased due to CHV/BXT port clock check improvemnts Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-and-tested-by:
Imre Deak <imre.deak@intel.com> Signed-off-by:
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Ville Syrjälä authored
CHV/BXT DPLL can't generate frequencies in the 216-240 MHz range. Account for that when checking whether the HDMI port clock is valid. This is particularly important for BXT since it can otherwise do 12bpc, and standard 1920x1080p60 CEA modes land right in the middle of that range when the clock gets multiplied to account for 12bpc. With the extra checks we will now filter out any mode where both 8bpc and 12bpc clock are within the gap. During modeset we then pick whichever mode works, favoring 12bpc if both are possible. 12bpc isn't supported on CHV so we simply end up filtering out any mode where the 8bpc port clock is in the gap. v2: Fix crtc_clock vs. port_clock fumble in compute_config() (Imre) Signed-off-by:
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Ville Syrjälä authored
Increase the HDMI port minimum port clock from 20 to 25 MHz. This is is the minimum listed in the DVI/HDMI specs, and it's also the documented minimum DPLL frequency for most of our platforms. Signed-off-by:
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Ville Syrjälä authored
Take the HDMI 12bpc mode and pixel repeat into account when extracting the dotclock from the hardware on DDI platforms. Tested on HSW only. Signed-off-by:
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Markus Elfring authored
The drm_property_unreference_blob() function tests whether its argument is NULL and then returns immediately. Thus the test around the call is not needed. This issue was detected by using the Coccinelle software. Signed-off-by:
Markus Elfring <elfring@users.sourceforge.net> Reviewed-by:
Zhao Junwang <zhjwpku@gmail.com> Signed-off-by:
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- 03 Jul, 2015 11 commits
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Daniel Vetter authored
Signed-off-by: -
Mika Kuoppala authored
Previously we have pointed the page where the individual ppgtt scratch structures refer to, to be the instance which GGTT setup have allocated. So it has been shared. To achieve full isolation between ppgtts also in this regard, allocate per ppgtt scratch page. Cc: Michel Thierry <michel.thierry@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by:
Michel Thierry <michel.thierry@intel.com> Signed-off-by:
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Gaurav K Singh authored
On CHT, changes are required for calculating the correct m,n & p with minimal error +/- for the required DSI clock, so that the correct dividor & ctrl values are written in cck regs for DSI. This patch has been tested on CHT RVP with 1200 x 1920 panel. v2 by Jani, rebased on earlier refactoring, original at [1]. [1] http://mid.gmane.org/1431368400-1942-5-git-send-email-rodrigo.vivi@intel.comSigned-off-by:
Gaurav K Singh <gaurav.k.singh@intel.com> Signed-off-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Reviewed-by:
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Gaurav K Singh authored
For MIPI panels requiring higher DSI clk, values needs to be added in lfsr_converts table for getting the correct values of pll ctrl and dividor values which gets programmed in cck regs, otherwise DSI PLL does not get locked leading to no display on the MIPI panel. Signed-off-by:
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Jani Nikula authored
Nuke three copies of the same switch case. Hopefully we can switch to a drm generic function later on, but that will require us to swich to enum mipi_dsi_pixel_format first. Reviewed-by:
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Paulo Zanoni authored
We first set the threshold value when we're allocating the CFB, and then later at {ilk,gen7}_fbc_enable() we increment it in case we're using 16bpp. While that is correct, it is dangerous: if we rework the code a little bit in a way that allows us to call intel_fbc_enable() without necessarily calling i915_gem_stolen_setup_compression() first, we might end up incrementing threshold more than once. To prevent that, increment a temporary variable instead. v2: Rebase. Signed-off-by:Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by:
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Tvrtko Ursulin authored
Currently only normal views were accounted which under-accounts the usage as reported in debugfs. Introduce new helper, i915_gem_obj_total_ggtt_size, and use it from call sites which want to know how much GGTT space are objects using. v2: Single loop in i915_gem_get_aperture_ioctl. (Chris Wilson) v3: Walk GGTT active/inactive lists in i915_gem_get_aperture_ioctl for better efficiency. (Chris Wilson, Daniel Vetter) v4: Make i915_gem_obj_total_ggtt_size private to debugfs. (Chris Wilson) v5: Change unsigned long to u64. (Chris Wilson) Signed-off-by:Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by:
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Mika Kuoppala authored
Every other alloc_* function return the pointer to the page they alloc. Follow the convention with scratch page also. Signed-off-by:
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Mika Kuoppala authored
Maintain base page handling functions in order of alloc, free, init. No functional changes. v2: s/Introduce/Maintain (Michel) v3: Rebase Cc: Michel Thierry <michel.thierry@intel.com> Signed-off-by:
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John Harrison authored
An earlier patch was added to reserve space in the ring buffer for the commands issued during 'add_request()'. The initial version was pessimistic in the way it handled buffer wrapping and would cause premature wraps and thus waste ring space. This patch updates the code to better handle the wrap case. It no longer enforces that the space being asked for and the reserved space are a single contiguous block. Instead, it allows the reserve to be on the far end of a wrap operation. It still guarantees that the space is available so when the wrap occurs, no wait will happen. Thus the wrap cannot fail which is the whole point of the exercise. Also fixed a merge failure with some comments from the original patch. v2: Incorporated suggestion by David Gordon to move the wrap code inside the prepare function and thus allow a single combined wait_for_space() call rather than doing one before the wrap and another after. This also makes the prepare code much simpler and easier to follow. v3: Fix for 'effective_size' vs 'size' during ring buffer remainder calculations (spotted by Tomas Elf). For: VIZ-5115 CC: Daniel Vetter <daniel@ffwll.ch> Signed-off-by:
John Harrison <John.C.Harrison@Intel.com> Reviewed-by:
Tomas Elf <tomas.elf@intel.com> Signed-off-by:
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Imre Deak authored
For the purpose of state checking we only care about the DPLL HW flags that we actually program, so mask off the ones that we don't. This fixes one set of DPLL state check failures. Signed-off-by:
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- 30 Jun, 2015 6 commits
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Imre Deak authored
Add support for reading out the HW state for DDI ports. Since the actual programming is very similar to the CHV/VLV DPIO PLL programming we can reuse much of the logic from there. This fixes the state checker failures I saw on my BXT with HDMI output. v2: - rebased on v2 of patch 4/5 Signed-off-by:
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Imre Deak authored
Depending on the platform the port clock fed to the pipe can be the PLL's post-divided fast clock rate or a /5 divided version of it. To make this more obvious across the platforms calculate this port clock along with the rest of the PLL parameters. This is also needed by the next patch where we can reuse the CHV helper for the BXT PLL HW readout code; so export the corresponding helper. While at it also add a more descriptive name to the helpers and a comment explaining what's being calculated. No functional change. Suggested-by:
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Imre Deak authored
Move the helper next to the PLL helpers of the other platforms for clarity. No functional change. Signed-off-by:
Sonika Jindal <sonika.jindal@intel.com> Signed-off-by:
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Imre Deak authored
Signed-off-by:
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Imre Deak authored
Although we have a fixed setting for the PLL9 and EBB4 registers, it still makes sense to check them together with the rest of PLL registers. While at it also remove a redundant comment about 10 bit clock enabling. Signed-off-by:
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David Weinehall authored
This patch adds support for 0.85V VccIO on Skylake Y, separate buffer translation tables for Skylake U, and support for I_boost for the entries that needs this. Changes in v2: * Refactored the code a bit to move all DDI signal level setup to intel_ddi.c Issue: VIZ-5677 Signed-off-by:
David Weinehall <david.weinehall@linux.intel.com> Reviewed-by:
Antti Koskipää <antti.koskipaa@linux.intel.com> [danvet: Apply style polish checkpatch suggested.] Signed-off-by:
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- 29 Jun, 2015 12 commits
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Ville Syrjälä authored
The hardware supposedly ignores the WM1 watermarks while the PND deadline mode is enabled, but clear out the register just in case. This is what the other OS does, and it does make register dumps look more consistent when we don't have partial WM1 values lingering in the registers (some WM1 watermarks already get zeroed when the actually used DSPFW registers get written). Signed-off-by:
Clint Taylor <Clinton.A.Taylor@intel.com> Signed-off-by:
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Ville Syrjälä authored
Allow tweaking the VLV/CHV memory latencies thorugh sysfs, like we do for ILK+. Signed-off-by:
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Ville Syrjälä authored
Enabling PM5/DDR DVFS with multiple active pipes isn't a validated configuration. It does seem to work most of the time at least, but there is clearly an additional risk of underruns, so let's not play with fire. Signed-off-by:
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Ville Syrjälä authored
CxSR (or maxfifo on VLV/CHV) blocks somne changes to the plane control register (enable bit at least, not quite sure about the rest). So in order to have the plane enable/disable when we want we need to first kick the hardware out of cxsr. Unfortunateloy this requires some extra vblank waits. For the CxSR enable after the plane update we should eventually use an async vblank worker, but since we don't have that just do sync vblank waits. For the disable case we have no choice but to do it synchronously. Signed-off-by:
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Ville Syrjälä authored
In order to get decnet memory self refresh residency on VLV, flip it over to the new CHV way of doing things. VLV doesn't do PM5 or DDR DVFS so it's a bit simpler. I'm not sure the currently memory latency used for CHV is really appropriate for VLV. Some further testing will probably be needed to figure that out. Signed-off-by:
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Ville Syrjälä authored
Consider which planes are active and compute the FIFO split based on the relative data rates. Since we only consider the pipe src width rather than the plane width when computing watermarks it seems best to do the same when computing the FIFO split as well. This means the only thing we actually have to consider for the FIFO splut is the bpp, and we can ignore the rest. I've just stuffed the logic into the watermark code for now. Eventually it'll need to move into the atomic update for the crtc. There's also one extra complication I've not yet considered; Some of the DSPARB registers contain bits related to multiple pipes. The registers are double buffered but apparently they update on the vblank of any active pipe. So doing the FIFO reconfiguration properly when multiple pipes are active is not going to be fun. But let's ignore that mess for now. Signed-off-by:
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Ville Syrjälä authored
Turns out the VLV/CHV system agent doesn't understand memory latencies, so trying to rely on the PND deadline mechanism is not going to fly especially when DDR DVFS is enabled. Currently we try to avoid the problems by lying to the system agent about the deadlines and setting the FIFO watermarks to 8 cachelines. This however leads to bad memory self refresh residency. So in order to satosfy everyone we'll just give up on the deadline scheme and program the watermarks old school based on the worst case memory latency. I've modelled this a bit on the ILK+ approach where we compute multiple sets of watermarks for each pipe (PM2,PM5,DDR DVFS) and when merge thet appropriate one later with the watermarks from other pipes. There isn't too much to merge actually since each pipe has a totally independent FIFO (well apart from the mess with the partially shared DSPARB registers), but still decopuling the pipes from each other seems like a good idea. Eventually we'll want to perform the watermark update in two phases around the plane update to avoid underruns due to the single buffered watermark registers. But that's still in limbo for ILK+ too, so I've not gone that far yet for VLV/CHV either. Signed-off-by:
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Ville Syrjälä authored
Read out the current watermark settings from the hardware at driver init time. This will allow us to compare the newly calculated values against the currrent ones and potentially avoid needless WM updates. Signed-off-by:
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Ville Syrjälä authored
Try to update the watermarks on the right side of the plane update. This is just a temporary hack until we get the proper two part update into place. However in the meantime this might have some chance of at least working. Signed-off-by:
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Ville Syrjälä authored
We want cxsr exit to happen ASAP, so toss in some POSTING_READ()s to make sure things are really kicked off. Signed-off-by:
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Daniel Vetter authored
We can't elide the fb tracking invalidate if the buffer is already in the right domain since that would lead to missed screen updates. I'm pretty sure I've written this already before but must have gotten lost unfortunately :( v2: Chris observed that all internal set_domain users already correctly do the fb invalidate on their own, hence we can move this just into the set_domain ioctl instead. v3: I screwed up setting the invalidate ORIGIN_* correctly (Chris). Cc: Chris Wilson <chris@chris-wilson.co.uk> Reported-by:
Daniel Vetter <daniel.vetter@intel.com> Reviewed-by:
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Rodrigo Vivi authored
We cannot let IPS enabled with no plane on the pipe: BSpec: "IPS cannot be enabled until after at least one plane has been enabled for at least one vertical blank." and "IPS must be disabled while there is still at least one plane enabled on the same pipe as IPS." This restriction apply to HSW and BDW. However a shortcut path on update primary plane function to make primary plane invisible by setting DSPCTRL to 0 was leting IPS enabled while there was no other plane enabled on the pipe causing flickerings that we were believing that it was caused by that other restriction where ips cannot be used when pixel rate is greater than 95% of cdclok. v2: Don't mess with Atomic path as pointed out by Ville. v3: Rebase after a long time and atomic path changes. Accept Ville suggestion of not check !fb v4: Re-factore on dinq Reference: https://bugs.freedesktop.org/show_bug.cgi?id=85583 Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by:Kenneth Graunke <kenneth@whitecape.org> [danvet: Make it compile] Signed-off-by:
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- 26 Jun, 2015 4 commits
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Damien Lespiau authored
We can't improve a 0 deviation, so when we find such a divider, skip the remaining ones they won't be better. This short-circuit the search for 34 of the 373 test frequencies in the corresponding i-g-t test (tools/skl_compute_wrpll) v2: Place the short-circuiting code in skl_compute_wrpll() (Paulo) (I'm sure nobody will notice the spurious removal of a blank line) Reviewed-by:
Damien Lespiau <damien.lespiau@intel.com> Signed-off-by:
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Bob Paauwe authored
Broxton is using a different register and different bit ordering for rps status capabilities. Also GT perf freqency register is different for Broxton so update that. Signed-off-by:
Bob Paauwe <bob.j.paauwe@intel.com> Reviewed-by:
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Damien Lespiau authored
Currently, if an odd divider improves the deviation (minimizes it), we take that divider. The recommendation is to prefer even dividers. v2: Move the check at the right place after having inverted the two for loops in the previous patch. Signed-off-by: -
Damien Lespiau authored
The HW validation team came back from further testing with a slightly changed constraint on the deviation between the DCO frequency and the central frequency. Instead of +-4%, it's now +1%/-6%. Unfortunately, the previous algorithm didn't quite cope with these new constraints, the reason being that it wasn't thorough enough looking at the possible divider candidates. The new algorithm looks at all dividers, which is definitely a hammer approach (we could reduce further the set of dividers to good ones as a follow up, at the cost of a bit more complicated code). But, at least, we can now satisfy the +1%/+6% rule for all the "Well known" HDMI frequencies of my test set (373 entries). On that subject, the new code is quite extensively tested in intel-gpu-tools (tools/skl_compute_wrpll). v2: Fix cycling between central frequencies and dividers (Paulo) Properly choose the minimal deviation between postive and negative candidates (Paulo). On the 373 test frequencies, v2 computes better dividers than v1 (ie more even dividers and lower deviation on average): v1: average deviation: 206.52 v2: average deviation: 194.47 Signed-off-by:
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