- 24 Dec, 2013 4 commits
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Laurent Pinchart authored
Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Laurent Pinchart authored
Signed-off-by:
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Laurent Pinchart authored
Signed-off-by:
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Laurent Pinchart authored
Now that the DTS file r8a7790-koelsch.dts can be used with board-koelsch.c and board-koelsch-reference.c, proceed with removing r8a7790-koelsch-reference.dts. Signed-off-by:
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- 19 Dec, 2013 25 commits
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Laurent Pinchart authored
Now that the DTS file r8a7790-lager.dts can be used with board-lager.c and board-lager-reference.c, proceed with removing r8a7790-lager-reference.dts. Signed-off-by:
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Laurent Pinchart authored
The external crystal frequency is 20MHz on the Koelsch board. Specify it in the device tree. Signed-off-by:
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Laurent Pinchart authored
The external crystal frequency is 20MHz on the Lager board. Specify it in the device tree. Signed-off-by:
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Laurent Pinchart authored
Copy the device nodes from Koelsch reference into the Koeslch device tree file. This will allow us to use a single DTS file regarless of kernel configuration. In case of legacy C board code the device nodes may or may not be used, but in the multiplatform case all the DT device nodes are used. Signed-off-by:
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Laurent Pinchart authored
Copy the device nodes from Lager reference into the Lager device tree file. This will allow us to use a single DTS file regarless of kernel configuration. In case of legacy C board code the device nodes may or may not be used, but in the multiplatform case all the DT device nodes are used. Signed-off-by:
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Laurent Pinchart authored
Declare all core clocks and DIV6 clocks, as well as all MSTP clocks currently used by r8a7791 boards. Signed-off-by:
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Laurent Pinchart authored
Reference clocks using a "clocks" property in all nodes corresponding to devices that require a clock. Signed-off-by:
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Laurent Pinchart authored
Declare all core clocks and DIV6 clocks, as well as all MSTP clocks currently used by r8a7790 boards. Signed-off-by:
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Laurent Pinchart authored
The board had 4 buttons connected to GPIOs, add a corresponding gpio-keys device. Signed-off-by:
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Laurent Pinchart authored
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Laurent Pinchart authored
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Laurent Pinchart authored
Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
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Laurent Pinchart authored
The Armadillo 800 EVA panel module has a backlight enable signal connected to GPIO 61. Report this in the backlight DT node. Signed-off-by:
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Laurent Pinchart authored
Commit 22ceeee1 ("pwm-backlight: Add power supply support") added a mandatory power supply for the PWM backlight. Add a fixed 5V regulator and reference it for the backlight power supply. Signed-off-by:
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Simon Horman authored
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Wolfram Sang authored
Signed-off-by:
Wolfram Sang <wsa@the-dreams.de> Signed-off-by:
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Simon Horman authored
The koelsch board uses has an SH ethernet controller which uses a Micrel phy. Select MICREL_PHY for koelsch if SH_ETH is enabled to make use of the Micrel-specific phy driver rather than relying on the generic phy driver. Signed-off-by: -
Simon Horman authored
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Simon Horman authored
Linux 3.13-rc3 Conflicts: drivers/pinctrl/sh-pfc/pfc-r8a7740.c drivers/pinctrl/sh-pfc/pfc-sh7372.c
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Simon Horman authored
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Simon Horman authored
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Simon Horman authored
This is a commit from the for-next branch of Linus Walleij's pin control tre git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git It is the oldest commit in that branch that provides the dependencies needed for SoC changes to the usage of sh-pfc.
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Laurent Pinchart authored
When CONFIG_COMMON_CLOCK is enabled, call rcar_gen2_clocks_init() in the timer init function to initialize the common clock framework before initializing the clock sources. This will take care of clock initialization when the r8a779[01] boards will be switched to multiplatform kernels. Signed-off-by:
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Laurent Pinchart authored
Add macros usable by device tree sources to reference r8a7791 clocks by index. Signed-off-by:
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Laurent Pinchart authored
Add macros usable by device tree sources to reference r8a7790 clocks by index. Signed-off-by:
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- 18 Dec, 2013 1 commit
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Laurent Pinchart authored
Prepare the clock at probe time, as there is no other appropriate place in the driver where we're allowed to sleep. Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: linux-kernel@vger.kernel.org Signed-off-by:
Daniel Lezcano <daniel.lezcano@linaro.org>
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- 14 Dec, 2013 3 commits
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Ben Dooks authored
The PCI sub-system is not enabled by default on ARM and on certain Renesas devices the build does not select it. This means that there are configurations that do not allow the AHB-PCI bridge used for the USB sub-systems to be built. For the R8A7790, R8A7791 and EMEV-2 select MIGHT_HAVE_PCI to allow the PCI drivers to be built. Also select MIGHT_HAVE_PCI for the multi-config where there may be many Reneasas devices selected. Reviewed-by:
Ian Molton <ian.molton@codethink.co.uk> Signed-off-by:
Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by:
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Laurent Pinchart authored
Turn clk_enable() and clk_disable() calls into clk_prepare_enable() and clk_disable_unprepare() to get ready for the migration to the common clock framework. Signed-off-by:
Magnus Damm <damm@opensource.se> Acked-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by:
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Laurent Pinchart authored
The break timer accesses hardware registers and thus requires the port to be enabled. It currently ensures this by enabling the port at the beginning of the timer handler, and disabling it at the end. However, the enable/disable operations call the runtime PM sync functions, which are not allowed in atomic context. The current situation is thus broken. This change relies on non-atomic code to enable/disable the port. The break timer will only be started from the IRQ handler, which already runs with the port enabled. We just need to ensure that the port won't be disabled with the timer running, and that's easily done by just cancelling the timer in the port disable function. Signed-off-by:
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- 13 Dec, 2013 3 commits
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Laurent Pinchart authored
MSTP clocks are gate clocks controlled through a register that handles up to 32 clocks. The register is often sparsely populated. Those clocks are found on Renesas ARM SoCs. Signed-off-by:
Mike Turquette <mturquette@linaro.org>
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Laurent Pinchart authored
DIV6 clocks are divider gate clocks controlled through a single register. The divider is expressed on 6 bits, hence the name, and can take values from 1/1 to 1/64. Those clocks are found on Renesas ARM SoCs. Signed-off-by:
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Laurent Pinchart authored
The R-Car Gen2 SoCs (R8A7790 and R8A7791) have several clocks that are too custom to be supported in a generic driver. Those clocks can be divided in two categories: - Fixed rate clocks with multiplier and divisor set according to boot mode configuration - Custom divider clocks with SoC-specific divider values This driver supports both. Signed-off-by:
Kumar Gala <galak@codeaurora.org> Signed-off-by:
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- 12 Dec, 2013 4 commits
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Laurent Pinchart authored
On non-DT platforms IRQ controllers associated with the GPIOs have a fixed IRQ base value known at compile time. The sh-pfc driver translates GPIO number to IRQ numbers using a hardcoded table. This mechanism breaks on DT platforms, as the IRQ base values are dynamic in that case. Fix this by specifying IRQs associated with GPIOs in IRQ resources, populated automatically from the device tree. When IRQ resources are specified the driver requires one IRQ resource per GPIO able to generate an interrupt, and uses the translation table to compute the IRQ resource offset instead of the IRQ number. Cc: devicetree@vger.kernel.org Signed-off-by:
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Laurent Pinchart authored
There's more than one window, name the field windows. Signed-off-by:
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Laurent Pinchart authored
This makes catching duplicate entries easier. Merge the two IRQ9 entries found after sorting. Signed-off-by:
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Laurent Pinchart authored
The external IRQ15 input multiplexed on GPIO 0 is missing. Add it. Signed-off-by:
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