- 25 Feb, 2019 2 commits
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git://git.infradead.org/linux-mtdBoris Brezillon authored
NAND core changes: - Fourth batch of fixes/cleanup to the raw NAND core impacting various controller drivers (Sunxi, Marvell, MTK, TMIO, OMAP2). - Checking the return code of nand_reset() and nand_readid_op(). - Removing ->legacy.erase and single_erase(). - Simplifying the locking. - Several implicit fall through annotations. Raw NAND controllers drivers changes: - Fixing various possible object reference leaks (MTK, JZ4780, Atmel). - ST: * Adding support for STM32 FMC2 NAND flash controller. - Meson: * Adding support for Amlogic NAND flash controller. - Denali: * Several cleanup patches. - Sunxi: * Several cleanup patches. - FSMC: * Disabling NAND on remove(). * Resetting NAND timings on resume(). SPI-NAND drivers changes: - Toshiba: * Adding support for all Toshiba products. - Macronix: * Fixing ECC status read. - Gigadevice: * Adding support for GD5F1GQ4UExxG.
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git://git.infradead.org/linux-mtdBoris Brezillon authored
SPI NOR Changes Core changes: - Add support of octal mode I/O transfer - Add a bunch of SPI NOR entries to the flash_info table SPI NOR controller driver changes: - cadence-quadspi: * Add support for Octal SPI controller * write upto 8-bytes data in STIG mode - mtk-quadspi: * rename config to a common one * add SNOR_HWCAPS_READ to spi_nor_hwcaps mask MAINTAINERS: - Add Tudor as SPI-NOR co-maintainer
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- 21 Feb, 2019 5 commits
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Bean Huo authored
Change SNOR_HWCPAS_READ_OCTAL to SNOR_HWCAPS_READ_OCTAL. Signed-off-by:
Bean Huo <beanhuo@micron.com> Reviewed-by:
Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by:
Boris Brezillon <boris.brezillon@collabora.com>
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Colin Ian King authored
There is a spelling mistake in a dev_error message. Fix it. Signed-off-by:
Colin Ian King <colin.king@canonical.com> Reviewed-by:
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Roger Pueyo Centelles authored
The Eon EN25QH64 is a 64 Mbit SPI NOR flash memory chip found on recent wireless routers. Its 32, 128 and 256 Mbit siblings are already supported. Tested on a COMFAST CF-E120A v3 router board. Signed-off-by:
Roger Pueyo Centelles <roger.pueyo@guifi.net> Reviewed-by:
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Frieder Schrempf authored
This adds support for the Macronix MX25V8035F, a 8Mb SPI NOR chip. It is used on i.MX6UL/ULL SoMs by Kontron Electronics GmbH (N631x). It was only tested with a single data line connected, by writing and reading random data with dd. Signed-off-by:
Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by:
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Frieder Schrempf authored
This adds support for the EON EN25Q80A, a 8Mb SPI NOR chip. It is used on i.MX6 boards by Kontron Electronics GmbH (N60xx, N61xx). It was only tested with a single data line connected, by writing and reading random data with dd. Signed-off-by:
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- 13 Feb, 2019 3 commits
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Vignesh R authored
Cadence OSPI controller IP supports Octal IO (x8 IO lines), It also has an integrated PHY. IP register layout is very similar to existing QSPI IP except for additional bits to support Octal and Octal DDR mode. Therefore, extend current driver to support Octal mode. Only Octal SDR read (1-1-8)mode is supported for now. Tested with mt35xu512aba Octal flash on TI's AM654 EVM. Signed-off-by:
Vignesh R <vigneshr@ti.com> Reviewed-by:
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Vignesh R authored
AM654 SoC has Cadence Octal SPI controller, which is similar to Cadence QSPI controller but supports Octal IO(x8 data lines) and Double Data Rate(DDR) mode. Add new compatible to support OSPI controller on TI's AM654 SoCs. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Ahmet Celenk authored
Due to two different versions (S25FL128SAGBHI200 and S25FL128SAGBHI210) of the s25fl128s qspi memory, the single "s25fl128s" device entry must be split into two to match the correct JEDEC ID's for each version. Solves paging related issues of S25FL128SAGBHI210 chips. Signed-off-by:
Ahmet Celenk <ahmet.celenk@procenne.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Marek Vasut <marek.vasut@gmail.com> Reviewed-by:
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- 10 Feb, 2019 2 commits
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Purna Chandra Mandal authored
cadence-quadspi controller allows upto eight bytes of data to be written in software Triggered Instruction generator (STIG) mode of operation. Lower 4 bytes are written through writedatalower and upper 4 bytes by writedataupper register. This patch allows all the 8 bytes to be written. Signed-off-by:
Purna Chandra Mandal <purna.chandra.mandal@intel.com> Reviewed-by:
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André Valentin authored
The mx25u3235f is found on the ZyXEL NBG6817 router, therefore add driver support for it so that we can upstream board support. Minimal tested with u-boot tools fw_printenv/fw_setenv on GlobalScale ESPRESSObin v5 board. Signed-off-by:
André Valentin <avalentin@marcant.net> [miyatsu@qq.com: Remove unnecessary white space.] Signed-off-by:
Ding Tao <miyatsu@qq.com> Reviewed-by:
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- 07 Feb, 2019 4 commits
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Masahiro Yamada authored
Commit 6f1fe97b ("mtd: rawnand: denali_dt: add more clocks based on IP datasheet") introduced a more correct binding that requires three named clocks. Now that all upstream DT files migrated over to it, remove the single anonymous clock support. Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by:
Dinh Nguyen <dinguyen@kernel.org> Acked-by:
Miquel Raynal <miquel.raynal@bootlin.com>
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Wen Yang authored
of_find_device_by_node() takes a reference to the struct device when it finds a match via get_device, there is no need to call get_device() twice. We also should make sure to drop the reference to the device taken by of_find_device_by_node() on driver unbind. Fixes: 1d6b1e46 ("mtd: mediatek: driver for MTK Smart Device") Signed-off-by:
Wen Yang <yellowriver2010@hotmail.com> Signed-off-by:
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Wen Yang authored
of_find_device_by_node() takes a reference to the struct device when it finds a match via get_device, there is no need to call get_device() twice. We also should make sure to drop the reference to the device taken by of_find_device_by_node() on driver unbind. Fixes: ae02ab00 ("mtd: nand: jz4780: driver for NAND devices on JZ4780 SoCs") Signed-off-by:
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Wen Yang authored
of_find_device_by_node() takes a reference to the struct device when it finds a match via get_device, there is no need to call get_device() twice. We also should make sure to drop the reference to the device taken by of_find_device_by_node() on driver unbind. Fixes: f88fc122 ("mtd: nand: Cleanup/rework the atmel_nand driver") Signed-off-by:
Boris Brezillon <bbrezillon@kernel.org> Reviewed-by:
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- 05 Feb, 2019 24 commits
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Linus Walleij authored
This disables the NAND on remove() and the errorpath, making sure the chipselect gets deasserted when the NAND is not in use. Cc: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
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Linus Walleij authored
When we go through a suspend/resume cycle the NAND timings and other settings may have been lost so reset the chip to bring it up in a known working state. The FSMC only supports single CS chips so we only need to call nand_reset(chip, 0). Cc: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by:
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Stefan Roese authored
Add support for GigaDevice GD5F1GQ4UExxG SPI NAND chip. Signed-off-by:
Stefan Roese <sr@denx.de> Cc: Chuanhong Guo <gch981213@gmail.com> Cc: Frieder Schrempf <frieder.schrempf@kontron.de> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Boris Brezillon <bbrezillon@kernel.org> Reviewed-by:
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Masahiro Yamada authored
This is a leftover of commit 997cde2a ("mtd: nand: denali: skip driver internal bounce buffer when possible"). Signed-off-by:
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Masahiro Yamada authored
This argument is not used at all. Signed-off-by:
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Masahiro Yamada authored
This code was added by commit 26d266e1 ("mtd: nand: denali: fix raw and oob accessors for syndrome page layout"), but I do not see sensible reason. The IRQ flags are correctly reset by denali_cmd_ctrl(), so this code is unneeded. Signed-off-by:
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Masahiro Yamada authored
nand_scan_ident() iterates over maxchips to find as many homogeneous chips as possible. Since commit 2d472aba ("mtd: nand: document the NAND controller/NAND chip DT representation"), new drivers should pass in the exact number of CS lines instead of possible max, but old platforms may still rely on nand_scan_ident() to detect the actual number of connected CS lines. In that case, this loop bails out when manufacturer or device ID unmatches. The reason of unmatch is most likely no chip is connected to that CS line. If so, nand_reset() should already have failed, and the following nand_readid_op() is pointless. Before ->exec_op hook was introduced, drivers had no way to tell the failure of NAND_CMD_RESET to the framework because the legacy ->cmdfunc() has void return type. Now drivers implementing ->exec_op hook can return the error code. You can save nand_readid_op() by checking the return value of nand_reset(). The return value of nand_readid_op() should be checked as well. If it fails, probably id[0] and id[1] are undefined values. Just for consistency, it should be sensible to check the return code in nand_do_write_oob() as well. Signed-off-by:
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Masahiro Yamada authored
Now that the last user of this hook, denali.c, stopped using it, we can remove the erase hook from nand_legacy. I squashed single_erase() because only the difference between single_erase() and nand_erase_op() is the number of bit shifts. The status/ret conversion in nand_erase_nand() is unneeded since commit eb94555e ("mtd: nand: use usual return values for the ->erase() hook"). Cleaned it up now. Signed-off-by:
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Masahiro Yamada authored
Commit f9ebd1bb ("mtd: rawnand: Deprecate ->erase()") discouraged the use of this hook, so I am happy to follow the suggestion. Although the Denali IP provides a special MAP10 command for erasing, using it would not buy us much. The Denali IP actually works with the generic erasing by single_erase() + ->cmdfunc hook (nand_command_lp) + ->cmd_ctrl hook (denali_cmd_ctrl). This method is also deprecated, but denali_erase() can go away irrespective of ->exec_op conversion. Signed-off-by:
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Mathieu Malaterre authored
There is a plan to build the kernel with -Wimplicit-fallthrough and these places in the code produced warnings (W=1). This commit removes the following warnings: drivers/mtd/nand/raw/nand_base.c:5556:6: warning: this statement may fall through [-Wimplicit-fallthrough=] drivers/mtd/nand/raw/nand_base.c:5575:6: warning: this statement may fall through [-Wimplicit-fallthrough=] drivers/mtd/nand/raw/nand_base.c:5613:13: warning: this statement may fall through [-Wimplicit-fallthrough=] Signed-off-by:
Mathieu Malaterre <malat@debian.org> Signed-off-by:
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Mathieu Malaterre authored
There is a plan to build the kernel with -Wimplicit-fallthrough and these places in the code produced warnings (W=1). This commit removes the following warnings: drivers/mtd/nand/raw/nand_legacy.c:332:6: warning: this statement may fall through [-Wimplicit-fallthrough=] drivers/mtd/nand/raw/nand_legacy.c:483:3: warning: this statement may fall through [-Wimplicit-fallthrough=] Signed-off-by:
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Yoshio Furuyama authored
Add device table for Toshiba Memory products. Also, generalize OOB layout structure and function names. Signed-off-by:
Yoshio Furuyama <tmcmc-mb-yfuruyama7@ml.toshiba.co.jp> Reviewed-by:
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Jianxin Pan authored
Add entry for Amlogic NAND controller driver and its bindings[0]. [0] https://lore.kernel.org/lkml/1547566684-57472-1-git-send-email-jianxin.pan@amlogic.com/Signed-off-by:
Liang Yang <liang.yang@amlogic.com> Signed-off-by:
Jianxin Pan <jianxin.pan@amlogic.com> Signed-off-by:
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Liang Yang authored
Add initial support for the Amlogic NAND flash controller which is available on Meson SoCs. Signed-off-by:
Yixun Lan <yixun.lan@amlogic.com> Signed-off-by:
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Liang Yang authored
Add Amlogic NAND controller dt-bindings for Meson SoC, Current this driver support GXBB/GXL/AXG platform. Signed-off-by:
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Boris Brezillon authored
nand_get_device() was complex for apparently no good reason. Let's replace this locking scheme with 2 mutexes: one attached to the controller and another one attached to the chip. Every time the core calls nand_get_device(), it will first lock the chip and if the chip is not suspended, will then lock the controller. nand_release_device() will release both lock in the reverse order. nand_get_device() can sleep, just like the previous implementation, which means you should never call that from an atomic context. We also get rid of - the chip->state field, since all it was used for was flagging the chip as suspended. We replace it by a field called chip->suspended and directly set it from nand_suspend/resume() - the controller->wq and controller->active fields which are no longer needed since the new controller->lock (now a mutex) guarantees that all operations are serialized at the controller level - panic_nand_get_device() which would anyway be a no-op. Talking about panic write, I keep thinking the rawnand implementation is unsafe because there's not negotiation with the controller to know when it's actually done with it's previous operation. I don't intend to fix that here, but that's probably something we should look at, or maybe we should consider dropping the ->_panic_write() implementation Last important change to mention: we now return -EBUSY when someone tries to access a device that as been suspended, and propagate this error to the upper layer. Signed-off-by:
Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by:
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Boris Brezillon authored
We are about to simplify the locking in the rawnand framework, and part of this simplication is about getting rid of chip->state, so let's first patch drivers that check the state. All of them do that to get a timeout value based on the operation that is being executed. Since a timeout is, by definition, something that is here to prevent hanging on an event that might never happen, picking the maximum timeout value no matter the operation should be harmless. Signed-off-by:
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Boris Brezillon authored
Stop initializing omap_gpmc_controller fields are declaration time and replace that by a call to nand_controller_init(). Since the same object might be shared by several NAND chips and the NAND controller driver expects a ->probe() per-chip, we need to keep track of the omap_gpmc_controller state (whether it's already been initialized or not). Signed-off-by:
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Boris Brezillon authored
nand_controller->wq has never been meant to be used by NAND controller drivers. This waitqueue is used by the framework to serialize accesses to a NAND controller, and messing up with its state is a really bad idea. Declare a completion object in tmio_nand and use it to wait for RB transitions. Signed-off-by:
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Boris Brezillon authored
nand_controller_init() has been added to simplify nand_controller struct initialization. Use this function instead of duplicating the logic. Signed-off-by:
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Gustavo A. R. Silva authored
One of the more common cases of allocation size calculations is finding the size of a structure that has a zero-sized array at the end, along with memory for some number of elements for that array. For example: struct foo { int stuff; void *entry[]; }; instance = devm_kzalloc(dev, sizeof(struct foo) + sizeof(void *) * count, GFP_KERNEL); Instead of leaving these open-coded and prone to type mistakes, we can now use the new struct_size() helper: instance = devm_kzalloc(dev, struct_size(instance, entry, count), GFP_KERNEL); This code was detected with the help of Coccinelle. Signed-off-by:Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by:
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Boris Brezillon authored
In non-EDO, tREA should be less than tRP to guarantee that the controller does not sample the IO lines too early. Unfortunately, the sunxi NAND controller does not allow us to have different values for tRP and tREH (tRP = tREH = tRW / 2). We have 2 options to overcome this limitation: 1/ Extend tRC to fulfil the tREA <= tRC / 2 constraint 2/ Use EDO mode (only works if timings->tRLOH > 0) Signed-off-by:
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Emil Lenngren authored
The datasheet specifies the upper four bits are reserved. Testing on real hardware shows that these bits can indeed be nonzero. Signed-off-by:
Emil Lenngren <emil.lenngren@gmail.com> Reviewed-by:
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Boris Brezillon authored
Fix the struct description and use standard kernel-doc header format (even if the file is not parsed by the doc generator). We also replace tabs by a single space. Signed-off-by:
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