- 11 Dec, 2018 4 commits
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Nicholas Kazlauskas authored
[Why] These properties aren't being carried over when the atomic state. This tricks atomic check and commit tail into performing underscan and scaling operations when they aren't needed. With the patch that forced scaling/RMX_ASPECT on by default this results in many unnecessary surface updates and hangs under certain conditions. [How] Duplicate the properties. Fixes: 91b66c47 ("drm/amd/display: Set RMX_ASPECT as default") Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] If the "max bpc" isn't explicitly set in the atomic state then it have a value of 0. This has the correct behavior of limiting a panel to 8bpc in the case where the panel supports 8bpc. In the case of eDP panels this isn't a true assumption - there are panels that can only do 6bpc. Banding occurs for these displays. [How] Initialize the max_bpc when the connector resets to 8bpc. Also carry over the value when the state is duplicated. Bugzilla: https://bugs.freedesktop.org/108825 Fixes: 307638884f72 ("drm/amd/display: Support amdgpu "max bpc" connector property") Signed-off-by:
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Nicholas Kazlauskas authored
This reverts commit 91b66c47. Forcing RMX_ASPECT as default uses the preferred/native mode's timings for any mode the user selects and scales the image. This provides a a consistently nicer result in the case where the selected mode's refresh rate matches the native mode's refresh but this isn't always the case. For example, if the monitor is 1080p@144Hz and the preferred mode is 60Hz then even if the user selects 1080p@144Hz as their selected mode they'll get 1080p@60Hz. Signed-off-by:
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Kuehling, Felix authored
This function was renamed in a previous commit. Update the stub function name for builds with CONFIG_HSA_AMD disabled. Fixes: 611736d8 ("drm/amdgpu: Add KFD VRAM limit checking") Acked-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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- 10 Dec, 2018 4 commits
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Alex Deucher authored
Add special avfs handling for some polaris variants. v2: fix copy paste typo. v3: fix asic rid check Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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YueHaibing authored
Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c: In function 'gfx_v8_0_pre_soft_reset': drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c:4950:27: warning: variable 'srbm_soft_reset' set but not used [-Wunused-but-set-variable] drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c: In function 'gfx_v8_0_post_soft_reset': drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c:5054:27: warning: variable 'srbm_soft_reset' set but not used [-Wunused-but-set-variable] It never used since introduction in commit d31a501e ("drm/amdgpu: add pre_soft_reset ip func") and e4ae0fc3 ("drm/amdgpu: implement gfx8 post_soft_reset") Reviewed-by:
Chunming Zhou <david1.zhou@amd.com> Signed-off-by:
YueHaibing <yuehaibing@huawei.com> Signed-off-by:
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Rex Zhu authored
driver need to reserve resource for each ctx for some hw features. so add this limitation. Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Tiecheng Zhou authored
RLC will go wrong in soft_reset under sriov Workaroound: only need to init RLC csb, and skip RLC stop, reset, start this is because host-driver has already done full initialization on RLC v2: squash in build fix Signed-off-by:Tiecehng Zhou <Tiecheng.Zhou@amd.com> Acked-by:
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- 07 Dec, 2018 20 commits
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Christian König authored
The GMC/VM subsystem is causing the faults, so move the handling here as well. Signed-off-by:
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Christian König authored
printk_ratelimit() is much better suited to limit the number of reported VM faults. Signed-off-by:
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Christian König authored
This allows us to filter out VM faults in the GMC code. v2: don't filter out all faults v3: fix copy&paste typo, send all IV to the KFD, don't change message level Signed-off-by:
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Felix Kuehling authored
This allows user mode to map doorbell pages into GPUVM address space. That way GPUs can submit to user mode queues (self-dispatch). Acked-by:
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Felix Kuehling authored
This is used for interoperability between ROCm compute and graphics APIs. It allows importing graphics driver BOs into the ROCm SVM address space for zero-copy GPU access. The API is split into two steps (query and import) to allow user mode to manage the virtual address space allocation for the imported buffer. Acked-by:
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Felix Kuehling authored
top_dev->gpu is NULL for CPUs. Avoid dereferencing it if NULL. Acked-by:
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Felix Kuehling authored
We don't want KFD processes evicting each other over VRAM usage. Therefore prevent overcommitting VRAM among KFD applications with a per-GPU limit. Also leave enough room for page tables on top of the application memory usage. Acked-by:
Eric Huang <JinHuiEric.Huang@amd.com> Signed-off-by:
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Kuehling, Felix authored
Avoid including mmu_context.h in amdgpu_amdkfd.h since that may be included in other header files that define traces. This leads to conflicts due to traces defined in other headers included via mmu_context.h. Acked-by:
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hersen wu authored
[WHY] clarify dal input parameters to pplib interface, remove un-used parameters. dal knows exactly which parameters needed and their effects at pplib and smu sides. current dal sequence for dcn1_update_clock to pplib: 1.smu10_display_clock_voltage_request for dcefclk 2.smu10_display_clock_voltage_request for fclk 3.phm_store_dal_configuration_data { set_min_deep_sleep_dcfclk set_active_display_count store_cc6_data --- this data never be referenced new sequence will be: 1. set_display_count --- need add new pplib interface 2. set_min_deep_sleep_dcfclk -- new pplib interface 3. set_hard_min_dcfclk_by_freq 4. set_hard_min_fclk_by_freq after this code refactor, smu10_display_clock_voltage_request, phm_store_dal_configuration_data will not be needed for rv. [HOW] step 1: add new functions at pplib interface step 2: add new functions at amdgpu dm and dc Signed-off-by:hersen wu <hersenxs.wu@amd.com> Reviewed-by:
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wentalou authored
amdgpu_ring_soft_recovery would have Call-Trace, when s_fence->parent was NULL inside amdgpu_job_timedout. Check fence first, as drm_sched_hw_job_reset did. Signed-off-by:
Wentao Lou <Wentao.Lou@amd.com> Reviewed-by:
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Xiangliang Yu authored
PSP ring need to be destroy before starting reinit for vf. This patche move it from hypervisor driver into guest. Signed-off-by:
Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by:
Frank Min <Frank.Min@amd.com> Acked-by:
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Xiangliang Yu authored
PSP only support VMR ring for SRIOV vf since v45 and all commands will be send to VMR ring for executing. VMR ring use C2PMSG 101 ~ 103 instead of C2PMSG 64 ~ 71. Signed-off-by:
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Xiangliang Yu authored
If PSP FW is running already, driver will not load PSP FW again and skip it. So psp fw version is not correct if reading it from FW binary file, need to get right version from register. Signed-off-by:
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Christian König authored
This allows us to drop the extra reserve in TTM. Signed-off-by:
Michel Dänzer <michel.daenzer@amd.com> Reviewed-by:
Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Christian König authored
And drop the now superflous extra reservations. Signed-off-by:
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Christian König authored
It is perfectly possible that the BO list is created before the BO is exported. While at it clean up setting shared to one instead of true. v2: add comment and simplify logic Signed-off-by:
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Christian König authored
Let's support simultaneous submissions to multiple engines. v2: rename the field to num_shared and fix up all users v3: rebased Signed-off-by:
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Aaron Liu authored
For Picasso && AM4 SOCKET board, we use picasso_rlc_am4.bin For Picasso && FP5 SOCKET board, we use picasso_rlc.bin Judgment method: PCO AM4: revision >= 0xC8 && revision <= 0xCF or revision >= 0xD8 && revision <= 0xDF otherwise is PCO FP5 Signed-off-by:Aaron Liu <aaron.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher at amd.com> Reviewed-by: Huang Rui <ray.huang at amd.com> Signed-off-by:
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Alex Deucher authored
Check if the MC firmware supports FFC and tell the SMC so mclk switching is handled properly. Reviewed-by:
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Alex Deucher authored
Add new messages for polaris. Reviewed-by:
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- 05 Dec, 2018 8 commits
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Sharat Masetty authored
This patch adds two new functions to help client drivers suspend and resume the scheduler job timeout. This can be useful in cases where the hardware has preemption support enabled. Using this, it is possible to have the timeout active only for the ring which is active on the ringbuffer. This patch also makes the job_list_lock IRQ safe. Suggested-by:
Sharat Masetty <smasetty@codeaurora.org> Reviewed-by:
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Sharat Masetty authored
In cases where the scheduler instance is used as a base object of another driver object, it's not clear if the driver can call scheduler cleanup on the fail path. So, Set the sched->thread to NULL, so that the driver can safely call drm_sched_fini() during cleanup. Signed-off-by:
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Wen Yang authored
kfree(NULL) is safe, so removes NULL check before freeing the mem. This patch also fix the ifnullfree.cocci warnings. Reviewed-by:
Lyude Paul <lyude@redhat.com> Signed-off-by:
Wen Yang <wen.yang99@zte.com.cn> CC: Alex Deucher <alexander.deucher@amd.com> CC: christian.koenig@amd.com CC: "David (ChunMing) Zhou" <David1.Zhou@amd.com> CC: David Airlie <airlied@linux.ie> (maintainer:DRM DRIVERS) CC: Lyude Paul <lyude@redhat.com> CC: Rex Zhu <Rex.Zhu@amd.com> CC: Jim Qu <Jim.Qu@amd.com> CC: amd-gfx@lists.freedesktop.org CC: dri-devel@lists.freedesktop.org Signed-off-by:
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Leo Li authored
In particular, we need the mmMC_VM_XGMI_LFB_CNTL register, for determining if xGMI is enabled on VG20. This will be used by DC to determine the correct spread spectrum adjustment for display and audio clocks. Reviewed-by:
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Alex Deucher authored
SI does not use doorbells, move asic doorbell init later asic check. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=108920Reviewed-by:
Oak Zeng <Oak.Zeng@amd.com> Signed-off-by:
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Alex Deucher authored
Adjust limits for newer polaris variants. v2: fix polaris11 kicker (Jerry) Reviewed-by:
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Alex Deucher authored
Update switch limit on newer polaris variants. This may fix flickering with high refresh rates with mclk switching enabled. Reviewed-by:
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David Francis authored
[Why] Tracing is a useful and cheap debug functionality [How] This creates a new trace system amdgpu_dm, currently with three trace events amdgpu_dc_rreg and amdgpu_dc_wreg report the address and value of any dc register reads and writes amdgpu_dc_performance requires at least one of those two to be enabled. It counts the register reads and writes since the last entry v2: Don't check for NULL before kfree Signed-off-by:
David Francis <David.Francis@amd.com> Reviewed-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
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- 04 Dec, 2018 1 commit
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Andrey Grodzovsky authored
amdgpu_xgmi_update_topology is called both on device registration and reset. Fix misleading print since the device is added only once to the hive on registration and not on reset. Signed-off-by:
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- 03 Dec, 2018 3 commits
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Andrey Grodzovsky authored
Use per hive wq to concurrently send reset commands to all nodes in the hive. v2: Switch to system_highpri_wq after dropping dedicated queue. Fix non XGMI code path KASAN error. Stop the hive reset for each node loop if there is a reset failure on any of the nodes. Signed-off-by:
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Andrey Grodzovsky authored
XGMI hive has some resources allocted on device init which needs to be deallocated when the device is unregistered. v2: Remove creation of dedicated wq for XGMI hive reset. v3: Use the gmc.xgmi.supported flag Signed-off-by:
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Andrey Grodzovsky authored
No point in use mdelay unless running from interrupt context (which we are not) This is busy wait which will block the CPU for the entirety of the wait time. Also, reduce wait time to 500ms as it is done in refernce code because 1s might cause PSP FW TO issues during XGMI hive reset. Signed-off-by:
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