- 05 Oct, 2023 14 commits
-
-
Kuninori Morimoto authored
Add initial support for the R-Car S4 Starter Kit with R8A779F4 SoC support. Based on a patch in the BSP. Signed-off-by:
Michael Dege <michael.dege@renesas.com> Signed-off-by:
Yusuke Goda <yusuke.goda.sx@renesas.com> Signed-off-by:
Tam Nguyen <tam.nguyen.xa@renesas.com> Signed-off-by:
Hai Pham <hai.pham.ud@renesas.com> Co-developed-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/87pm1wfn8z.wl-kuninori.morimoto.gx@renesas.comSigned-off-by:
-
Kuninori Morimoto authored
The R8A779F4 (R-Car S4-8) SoC is an updated version of R8A779F0. Add support for it, using the r8a779f0 .dtsi internally. Signed-off-by:
-
Claudiu Beznea authored
Add the initial device tree for the Renesas RZ/G3S SMARC EVK board. Signed-off-by:
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by:
-
Claudiu Beznea authored
Add the initial device tree for the RZ SMARC Carrier-II. At the moment it contains only the serial interface. Signed-off-by:
-
Claudiu Beznea authored
Add initial support for the RZ/G3S SMARC SoM. The following devices available on the SoM are added to this initial device tree: - RZ/G3S SoC: Renesas R9A08G045S33GBG - Clock Generator (only 24MHz output): Renesas 5L35023B - 1GiB LPDDR4 SDRAM: Micron MT53D512M16D1DS-046 - 64GB eMMC Flash (though SD ch0): Micron MTFC64GBCAQTC SD channel 0 of RZ/G3S is connected to an uSD card interface and an eMMC. The selection b/w them is done through a hardware switch. The DT will select b/w uSD and eMMC through the SW_SD0_DEV_SEL build flag. Signed-off-by:
-
Claudiu Beznea authored
Add the initial DTSI for the RZ/G3S SoC. The files in this commit have the following meaning: - r9a08g045.dtsi: RZ/G3S family SoC common parts - r9a08g045s33.dtsi: RZ/G3S R0A08G045S33 SoC specific parts Signed-off-by:
-
Geert Uytterhoeven authored
Renesas RZ/G3S DT Binding Definitions Clock definitions for the Renesas RZ/G3S (R9A08G045) SoC, shared by driver and DT source files.
-
Lad Prabhakar authored
Now that noncoherent dma support for the RZ/Five SoC has been added, enable the IP blocks which were disabled on the RZ/Five SMARC. This adds support for the below peripherals: * Ethernet * DMAC * SDHI * USB * RSPI * SSI Signed-off-by:
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by:
-
Lad Prabhakar authored
RZ/Five is a noncoherent SoC so to indicate this add dma-noncoherent property to RZ/Five SoC DTSI. Signed-off-by:
-
Lad Prabhakar authored
Add L2 cache node for RZ/Five SoC. Signed-off-by:
-
Geert Uytterhoeven authored
Add a device node for the Spansion S29GL512P NOR FLASH on the Bock-W development board. This FLASH resides in the external address space of the Local Bus State Controller. Signed-off-by:
-
Biju Das authored
Currently audio mclk uses a fixed clk of 11.2896MHz (multiple of 44.1kHz). Replace this fixed clk with the programmable versa3 clk that can provide the clocking to support both 44.1kHz (with a clock of 11.2896MHz) and 48kHz (with a clock of 12.2880MHz), based on audio sampling rate for playback and record. Signed-off-by:
Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by:
-
Geert Uytterhoeven authored
Merge tag 'clk-fixes-for-linus' of https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux into renesas-dts-for-v6.7 Adding versa3 clock generator nodes to DTS depends on the fixed clock index handling: - Fix the binding for versaclock3 that was introduced this merge window so we know what the values are for clk consumers
-
Claudiu Beznea authored
Add documentation for the RZ/G3S CPG. The RZ/G3S CPG module is almost identical to the one available in RZ/G2{L,UL}, the exception being some core clocks as follows: - The SD clock is composed of a mux and a divider, and the divider has some limitations (div = 1 cannot be set if mux rate is 800MHz), - There are 3 SD clocks, - The OCTA and TSU clocks are specific to RZ/G3S, - PLL1/4/6 are specific to RZ/G3S with its own computation formula. Even with this RZ/G3S could use the same bindings as RZ/G2L. Along with documentation bindings for the RZ/G3S (R9A08G045) Clock Pulse Generator (CPG) core clocks, module clocks and resets were added. Signed-off-by:Rob Herring <robh@kernel.org> Reviewed-by:
-
- 25 Sep, 2023 10 commits
-
-
Kuninori Morimoto authored
+-- ULCB -------------------+ |+--------+ +--------+| || SSI0| <---> |ak4613 || || SSI1| <---> | || || | +--------+| || | +--------+| || SSI2| <---> |HDMI || || | +--------+| || SSI3| <--+ | || SSI4| <-+| | |+--------+ || | +-------------||------------+ +-- Kingfisher -------------+ | || +--------+| | |+->|pcm3168a|| | +-->| || | +--------+| +---------------------------+ On UCLB/KF, we intuitively think we want to handle these as "2 Sound Cards": card0,0: 1st sound of ULCB (SSI0 - ak4613) card0,1: 2nd sound of ULCB (SSI2 - HDMI) card1,0: 1st sound of KF (SSI3 - pcm3168a) ^ ^ However, because of ASoC Component vs. Card framework limitations, we needed to handle this as "1 big Sound Card": card0,0: 1st sound of ULCB/KF (SSI0 - ak4613) card0,1: 2nd sound of ULCB/KF (SSI2 - HDMI) card0,2: 3rd sound of ULCB/KF (SSI3 - pcm3168a) ^ ^ Now ASoC supports multi Component, which allows us to handle "2 Sound Cards" such as "ULCB Sound Card" and "Kingfisher Sound Card", all ULCB/KF Audio dtsi can be updated. Note that this changes the Sound Card specification method from userland, especially for Kingfisher Sound. Signed-off-by:
-
Geert Uytterhoeven authored
Add device nodes for the dual Spansion S25FL512S QSPI NOR FLASH and the Spansion S29GL512S CFI NOR FLASH on the RSK+RZA1 development board. The former is mapped directly through the SPI Multi I/O Bus Controller. The latter resides in the external address space of the Bus State Controller (BSC). Signed-off-by:
-
Geert Uytterhoeven authored
Add device nodes for the dual Spansion S25FL512S QSPI NOR FLASH and the two Spansion S29GL512S CFI NOR FLASHes on the Genmai development board. The former is mapped directly through the SPI Multi I/O Bus Controller. The latter reside in the address space of the Bus State Controller (BSC). Signed-off-by:
-
Geert Uytterhoeven authored
The SMSC LAN89218AQ Ethernet controller on the Wheat development board resides in the external address space of the Local Bus State Controller (LBSC). Move the Ethernet device node to reflect this. Signed-off-by:
-
Geert Uytterhoeven authored
The SMSC LAN89218AQ Ethernet controller on the Blanche development board resides in the external address space of the Local Bus State Controller (LBSC). Move the Ethernet device node to reflect this. Signed-off-by:
-
Geert Uytterhoeven authored
The SMSC LAN89218AQ Ethernet controller on the Marzen development board resides in the external address space of the Local Bus State Controller (LBSC). Move the Ethernet device node to reflect this. Signed-off-by:
-
Geert Uytterhoeven authored
Add a minimal device node for the Local Bus State Controller (LBSC) on the R-Car V2H SoC, to be extended by board DTS files for devices residing in the LBSC external address space. Signed-off-by:
-
Geert Uytterhoeven authored
Add a minimal device node for the Local Bus State Controller (LBSC) on the R-Car H1 SoC, to be extended by board DTS files for devices residing in the LBSC external address space. Signed-off-by:
-
Geert Uytterhoeven authored
Add a minimal device node for the Bus State Controller (BSC) on the RZ/A1H SoC, to be extended by board DTS files for devices residing in the BSC external address space. Signed-off-by:
-
Geert Uytterhoeven authored
Several board DTS files contain minimal device nodes that represent on-SoC Local Bus State Controllers (LBSC), although they belong in the SoC-specific DTS files instead. As these device nodes are incomplete and unused, and hamper adding proper nodes later, it is better to just remove them. Signed-off-by:
-
- 12 Sep, 2023 1 commit
-
-
Timo Alho authored
tegra-bpmp clocks driver makes implicit conversion of signed error code to unsigned value in recalc_rate operation. The behavior for recalc_rate, according to it's specification, should be that "If the driver cannot figure out a rate for this clock, it must return 0." Fixes: ca6f2796 ("clk: tegra: Add BPMP clock driver") Signed-off-by:
Timo Alho <talho@nvidia.com> Signed-off-by:
Mikko Perttunen <mperttunen@nvidia.com> Link: https://lore.kernel.org/r/20230912112951.2330497-1-cyndis@kapsi.fiSigned-off-by:
Stephen Boyd <sboyd@kernel.org>
-
- 11 Sep, 2023 13 commits
-
-
Marek Vasut authored
Rework the write operation such that the Byte Count register is written with a single raw i2c write outside of regmap using transfer which does specify the number of bytes to be transfered, one in this case, and which makes the expected subsequent write transfer look like address+register+data, and then make use of this method. Without this change, the Byte Count register write in probe() would succeed as it would provide the byte count as part of its write payload, but any subsequent writes would fail due to this Byte Count register programming. Such failing writes happens e.g. during resume, when restoring the regmap content. Fixes: edc12763 ("clk: si521xx: Clock driver for Skyworks Si521xx I2C PCIe clock generators") Signed-off-by:
Marek Vasut <marex@denx.de> Link: https://lore.kernel.org/r/20230831181656.154750-2-marex@denx.deSigned-off-by:
-
Marek Vasut authored
In order to reload registers into the clock generator on resume using regcache_sync(), it is necessary to select one of the regcache types which are not NONE. Since this device has some 7 registers, use the simplest one, FLAT. The regcache code complains about REGCACHE_NONE being selected and generates a WARNING, this fixes that warning. Fixes: edc12763 ("clk: si521xx: Clock driver for Skyworks Si521xx I2C PCIe clock generators") Signed-off-by:
-
Zhifeng Tang authored
The thm*_clk have two clock sources 32k and 250k,excluding 32m. Fixes: af3bd365 ("clk: sprd: Add clocks support for UMS512") Signed-off-by:
Zhifeng Tang <zhifeng.tang@unisoc.com> Acked-by:
Chunyan Zhang <zhang.lyra@gmail.com> Reviewed-by:
Baolin Wang <baolin.wang@linux.alibaba.com> Link: https://lore.kernel.org/r/20230824092624.20020-1-zhifeng.tang@unisoc.comSigned-off-by:
-
Biju Das authored
Make vc3_clk_mux enum values depend upon vc3_clk enum values to avoid any accidental breakage in the future. Signed-off-by:
-
Biju Das authored
According to Table 3. ("Output Source") in the 5P35023 datasheet, the output clock mapping should be 0=REF, 1=SE1, 2=SE2, 3=SE3, 4=DIFF1, 5=DIFF2. But the code uses inverse. Fix this mapping issue. Suggested-by: -
Biju Das authored
Fix the below cocci warnings by replacing do_div()->div64_ul() and bound the result with a max value of U16_MAX. cocci warnings: drivers/clk/clk-versaclock3.c:404:2-8: WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead. Reported-by:
Julia Lawall <julia.lawall@inria.fr> Closes: https://lore.kernel.org/r/202307270841.yr5HxYIl-lkp@intel.com/ Fixes: 6e9aff55 ("clk: Add support for versa3 clock driver") Signed-off-by:
-
Biju Das authored
Add description for "#clock-cells" property to map indexes to the clock output in the Table 3. ("Output Source") in the 5P35023 datasheet (ie: {REF,SE1,SE2,SE3,DIFF1,DIFF2}. Also update the "assigned-clock-rates" in the example. While at it, replace clocks phandle in the example from x1_x2->x1 as X2 is a different 32768 kHz crystal. Suggested-by:Conor Dooley <conor.dooley@microchip.com> Acked-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230824104812.147775-2-biju.das.jz@bp.renesas.comReviewed-by:
-
Yoshihiro Shimoda authored
Enable PCIe Host controller channel 0 on R-Car S4-8 Spider board. Since this board has an Oculink connector, CLKREQ# pin of PFC for PCIe should not be used. So, using a GPIO is used to output the clock instead. Otherwise the controller cannot detect a PCIe device. Signed-off-by:
-
Yoshihiro Shimoda authored
Add PCIe Host and Endpoint nodes for R-Car S4-8 (R8A779F0). Signed-off-by:
-
Geert Uytterhoeven authored
The "probe-type" property was only needed when used with the (long obsolete) "direct-mapped" compatible value. Signed-off-by:
-
Geert Uytterhoeven authored
make dtbs_check: arch/arm/boot/dts/r8a73a4-ape6evm.dtb: flash@0: compatible: 'oneOf' conditional failed, one must be fixed: ['cfi-flash', 'mtd-rom'] is too long 'cfi-flash' is not one of ['amd,s29gl01gp', 'amd,s29gl032a', 'amd,s29gl256n', 'amd,s29gl512n', 'arm,versatile-flash', 'arm,vexpress-flash', 'cortina,gemini-flash', 'cypress,hyperflash', 'ge,imp3a-firmware-mirror', 'ge,imp3a-paged-flash', 'gef,ppc9a-firmware-mirror', 'gef,ppc9a-paged-flash', 'gef,sbc310-firmware-mirror', 'gef,sbc310-paged-flash', 'gef,sbc610-firmware-mirror', 'gef,sbc610-paged-flash', 'intel,28f128j3', 'intel,dt28f160', 'intel,ixp4xx-flash', 'intel,JS28F128', 'intel,JS28F640', 'intel,PC28F640P30T85', 'numonyx,js28f00a', 'numonyx,js28f128', 'sst,sst39vf320', 'xlnx,xps-mch-emc-2.00.a'] 'cfi-flash' is not one of ['cypress,cy7c1019dv33-10zsxi', 'arm,vexpress-psram'] 'mtd-rom' is not one of ['cfi-flash', 'jedec-flash'] 'mtd-ram' was expected From schema: Documentation/devicetree/bindings/mtd/mtd-physmap.yaml Signed-off-by: -
Geert Uytterhoeven authored
On blanche, the GPIO keyboard fails to probe with: sh-pfc e6060000.pinctrl: could not map pin config for "GP_11_02" Fix this by correcting the name for this pin to "GP_11_2". Fixes: 1f27fede ("ARM: dts: blanche: Configure pull-up for SOFT_SW and SW25 GPIO keys") Signed-off-by: -
Kuninori Morimoto authored
Renesas Sound has been using CPG_AUDIO_CLK_I on CPG_CORE for clock, but this was wrong. Instead, it needs to use CPG_MOD, so clk_i can handle the "ADG" bit in SMSTPCR9. Signed-off-by:
-
- 10 Sep, 2023 2 commits
-
-
Linus Torvalds authored
-
git://anongit.freedesktop.org/drm/drmLinus Torvalds authored
Pull drm ci scripts from Dave Airlie: "This is a bunch of ci integration for the freedesktop gitlab instance where we currently do upstream userspace testing on diverse sets of GPU hardware. From my perspective I think it's an experiment worth going with and seeing how the benefits/noise playout keeping these files useful. Ideally I'd like to get this so we can do pre-merge testing on PRs eventually. Below is some info from danvet on why we've ended up making the decision and how we can roll it back if we decide it was a bad plan. Why in upstream? - like documentation, testcases, tools CI integration is one of these things where you can waste endless amounts of time if you accidentally have a version that doesn't match your source code - but also like the above, there's a balance, this is the initial cut of what we think makes sense to keep in sync vs out-of-tree, probably needs adjustment - gitlab supports out-of-repo gitlab integration and that's what's been used for the kernel in drm, but it results in per-driver fragmentation and lots of duplicated effort. the simple act of smashing an arbitrary winner into a topic branch already started surfacing patches on dri-devel and sparking good cross driver team discussions Why gitlab? - it's not any more shit than any of the other CI - drm userspace uses it extensively for everything in userspace, we have a lot of people and experience with this, including integration of hw testing labs - media userspace like gstreamer is also on gitlab.fd.o, and there's discussion to extend this to the media subsystem in some fashion Can this be shared? - there's definitely a pile of code that could move to scripts/ if other subsystem adopt ci integration in upstream kernel git. other bits are more drm/gpu specific like the igt-gpu-tests/tools integration - docker images can be run locally or in other CI runners Will we regret this? - it's all in one directory, intentionally, for easy deletion - probably 1-2 years in upstream to see whether this is worth it or a Big Mistake. that's roughly what it took to _really_ roll out solid CI in the bigger userspace projects we have on gitlab.fd.o like mesa3d" * tag 'topic/drm-ci-2023-08-31-1' of git://anongit.freedesktop.org/drm/drm: drm: ci: docs: fix build warning - add missing escape drm: Add initial ci/ subdirectory
-
