- 08 Jun, 2016 2 commits
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Masahiro Yamada authored
My mistake in the initial support patches. Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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hongkun.cao authored
An irq which is a wake up source maybe masked unexpectedly if the wake up source irq was triggered after pinctrl irqchip suspend and before suspend_device_irqs finished. Use *_noirq callbacks to guarantee pinctrl irqchip suspend would be called after suspend_devices_irqs. Signed-off-by:
hongkun.cao <hongkun.cao@mediatek.com> Signed-off-by:
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- 31 May, 2016 29 commits
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Neil Armstrong authored
Rename pinctrl_utils_dt_free_map to pinctrl_utils_free_map, introduced in d32f7fd3 ("pinctrl: Rename pinctrl_utils_dt_free_map to pinctrl_utils_free_map") but not reported into oxnas driver. Fixes: 611dac1e ("pinctrl: Add Oxford Semiconductor OXNAS pinctrl and gpio driver") Signed-off-by:
Neil Armstrong <narmstrong@baylibre.com> Signed-off-by:
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Masahiro Yamada authored
Add pin configuration and pinmux support for UniPhier PH1-LD20 SoC. Signed-off-by:
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Masahiro Yamada authored
Add pin configuration and pinmux support for UniPhier PH1-LD11 SoC. Signed-off-by:
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Masahiro Yamada authored
Currently, the UniPhier pinctrl driver itself is a syscon, but it turned out much more reasonable to make it a child node of a syscon because our syscon node consists of a bunch of system configuration registers, not only pinctrl, but also phy, and misc registers. It is difficult to split the node. To allow to migrate to the new DT structure, this commit adds new compatible strings to not disturb the existing DT. After a while, the old binding will be removed. Signed-off-by:
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Masahiro Yamada authored
This is needed to get access to UniPhier System Bus (external bus). Signed-off-by:
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Masahiro Yamada authored
These pins do not support pin-muxing, but it is useful to support pin configuration for them. Signed-off-by:
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Masahiro Yamada authored
PH1-LD4 and PH1-sLD8 SoCs have pins that support pin configuration (pin biasing, drive strength control), but not pin-muxing. Allow to fill the mux value table with -1 for those pins; pins with mux value -1 will be skipped in the pin-mux set function. The mux value type should be changed from "unsigned" to "int" in order to accommodate -1 as a special case. Signed-off-by:
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Masahiro Yamada authored
Upcoming new pinctrl drivers for PH1-LD11 and PH-LD20 support input signal gating for each pin. (While, existing ones only support it per pin-group.) This commit updates the core part for that. Signed-off-by:
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Masahiro Yamada authored
The core part of the UniPhier pinctrl driver needs to support a new capability for upcoming UniPhier ARMv8 SoCs. This sometimes happens because pinctrl drivers include really SoC-specific stuff. This commit intends to tidy up SoC-specific parameters of the existing drivers before adding the new one. Having just one flag would be better than adding a new struct member every time a new SoC-specific capability comes up. At this time, there is one flag, UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE. This capability (I'd say rather quirk) was added for PH1-Pro4 and PH1-Pro5 as requirement from a customer. For those SoCs, one pin-mux setting is controlled by the combination of two separate registers; the LSB bits at register offset (8 * N) and the MSB bits at (8 * N + 4). Because it is impossible to update two separate registers atomically, the LOAD_PINCTRL register should be set in order to make the pin-mux settings really effective. Signed-off-by:
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Masahiro Yamada authored
Unfortunately, the pin number of the new SoC, PH1-LD11, is not contiguous. The base frame work must be adjusted to support the new SoC pinctrl driver. The pin_desc_get() exploits radix-tree for pin look-up, so it works more efficiently with sparse pin space. Signed-off-by:
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Masahiro Yamada authored
The new ARMv8 SoC, PH1-LD20, supports more fine-grained drive strength control. Drive strength of some pins are controlled by 3-bit width registers (8-level granularity). Signed-off-by:
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Masahiro Yamada authored
The new ARMv8 SoC, PH1-LD20, supports more fine-grained drive strength control. Some of the configuration registers on it have 3-bit width. The feature will be supported in the next commit, but a problem is that macro names are getting longer and longer in the current naming scheme. Before moving forward, this commit renames macros as follows: UNIPHIER_PIN_DRV_4_8 -> UNIPHIER_PIN_DRV_1BIT UNIPHIER_PIN_DRV_8_12_16_20 -> UNIPHIER_PIN_DRV_2BIT UNIPHIER_PIN_DRV_FIXED_4 -> UNIPHIER_PIN_DRV_FIXED4 UNIPHIER_PIN_DRV_FIXED_5 -> UNIPHIER_PIN_DRV_FIXED5 UNIPHIER_PIN_DRV_FIXED_8 -> UNIPHIER_PIN_DRV_FIXED8 Signed-off-by:
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Masahiro Yamada authored
Currently, every SoC driver defines struct pinctrl_desc statically, i.e. it consumes memory footprint even if it is not probed. In multi-platform, many pinctrl drivers are linked (generally as built-in objects), although only one of them is actually used. So, it is reasonable to allocate memory dynamically where possible. Signed-off-by:
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Masahiro Yamada authored
Every SoC driver sets the same name for struct pinctrl_desc and platform_driver. The common probe function can set desc->name instead of duplicating strings in each SoC driver. Signed-off-by:
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Masahiro Yamada authored
The owner of the struct pinctrl_desc matches that of platform_driver. Set it in the common probe function. Signed-off-by:
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Masahiro Yamada authored
These pin tables were generated by parsing hardware documents with a script, but the script had a bug. Fix the register offsets. Signed-off-by:
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Masahiro Yamada authored
Make function/variable names match the file names for consistency. Signed-off-by:
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Masahiro Yamada authored
Without this, reading the "pins" in the debugfs causes kernel BUG. Fixes: 6e908892 ("pinctrl: UniPhier: add UniPhier pinctrl core support") Signed-off-by:
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Peng Fan authored
To i.MX7D, there are two iomux controllers, iomuxc and iomuxc_lpsr. They should not share one pin controller descriptor, otherwise the value filled into imx_pinctrl_desc when probing the first iomux controller will be overridden when probing the second one. In this patch, discard the static allcoated imx_pinctrl_desc and switch to dynamically allcate pin controller descriptor for each iomux controller. Signed-off-by:
Peng Fan <van.freenix@gmail.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: Stefan Agner <stefan@agner.ch> Cc: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by:
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Kevin Hilman authored
Add EE domain pins for ethernet interface. Acked-by:
Carlo Caione <carlo@endlessm.com> Signed-off-by:
Kevin Hilman <khilman@baylibre.com> Signed-off-by:
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Kevin Hilman authored
Add EE domain pins for UART A, B & C. Acked-by:
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Kevin Hilman authored
Add EE domain pins for eMMC and SD card. Acked-by:
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Kevin Hilman authored
Add pins for some more AO domain devices: UART_AO_B and I2C master & slave. Acked-by:
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Masahiro Yamada authored
-ENOMEM is more suitable error code because kasprintf() fails in case of memory shortage. Signed-off-by:
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Masahiro Yamada authored
gc_pinctrl_remove() calls platform_get_drvdata(), but I see neither platform_set_drvdata() nor dev_set_drvdata() anywhere in this driver. Signed-off-by:
Baruch Siach <baruch@tkos.co.il> Signed-off-by:
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Masahiro Yamada authored
To improve debugfs readability, use commas instead of whitespaces for separating configuration parameters. For example, the "pinconf-pins" dump on my board will change as follows: Without this commit: # head -5 pinconf-pins Pin config settings per pin Format: pin (name): configs pin 0 (ED0): input bias pull down output drive strength (8 mA) input enabled pin 1 (ED1): input bias pull down output drive strength (8 mA) input enabled pin 2 (ED2): input bias pull down output drive strength (8 mA) input enabled With this commit: # head -5 pinconf-pins Pin config settings per pin Format: pin (name): configs pin 0 (ED0): input bias pull down, output drive strength (8 mA), input enabled pin 1 (ED1): input bias pull down, output drive strength (8 mA), input enabled pin 2 (ED2): input bias pull down, output drive strength (8 mA), input enabled Signed-off-by:
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Masahiro Yamada authored
Currently, struct pinctrl_pin_desc can have per-pin driver private data, but it is not copied to struct pin_desc. For a driver with sparse pin space, for-loop search like below would be necessary in order to get the driver-specific data for a desired pin number. for (i = 0; i < pctldev->desc->npins; i++) if (pin_number == pctldev->desc->pins[i].number) return pctldev->desc->pins[i].drv_data; This is not efficient for a driver with a large number of pins. So, copy the data to struct pin_desc when each pin is registered for the faster radix tree lookup. Signed-off-by: -
Masahiro Yamada authored
If a pin name is not specified in struct pinctrl_pin_desc, pinctrl_register_one_pin() dynamically assigns its name. So, desc->name is always a valid pointer here. Signed-off-by:
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Patrice Chotard authored
As these 2 functions code are 95% similar, factorize them. Signed-off-by:
Patrice Chotard <patrice.chotard@st.com> Acked-by:
Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by:
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- 30 May, 2016 8 commits
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Krzysztof Kozlowski authored
Although unbinding a pinctrl driver requires root privileges but it still might be used theoretically in certain attacks (by triggering NULL pointer exception or memory corruption). Samsung pincontrol drivers are essential for system operation so their removal is not expected. They do not implement remove() driver callback and they are not buildable as modules. Suppression of the unbinding will prevent triggering NULL pointer exception like this (Odroid XU3): $ echo 13400000.pinctrl > /sys/bus/platform/drivers/samsung-pinctrl/unbind $ cat /sys/kernel/debug/gpio Unable to handle kernel NULL pointer dereference at virtual address 00000c44 pgd = ec41c000 [00000c44] *pgd=6d448835, *pte=00000000, *ppte=00000000 Internal error: Oops: 17 [#1] PREEMPT SMP ARM (samsung_gpio_get) from [<c034f9a0>] (gpiolib_seq_show+0x1b0/0x26c) (gpiolib_seq_show) from [<c01fb8c0>] (seq_read+0x304/0x4b8) (seq_read) from [<c02dbc78>] (full_proxy_read+0x4c/0x64) (full_proxy_read) from [<c01d9fb0>] (__vfs_read+0x2c/0x110) (__vfs_read) from [<c01db400>] (vfs_read+0x8c/0x110) (vfs_read) from [<c01db4c4>] (SyS_read+0x40/0x8c) (SyS_read) from [<c01078c0>] (ret_fast_syscall+0x0/0x3c) Suggested-by:Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by:
Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by:
Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by:
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Neil Armstrong authored
Implement a get_direction callback for the OXNAS GPIO driver in order to have pin output polarity in debugfs and new userspace ABI. Signed-off-by:
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Laxman Dewangan authored
MAXIM Semiconductor's PMIC, MAX77620/MAX20024 has 8 GPIO pins which also act as the special function in alternate mode. Also there is configuration like push-pull, open drain, FPS timing etc for these pins. Add pin control driver to configure these parameters through pin control APIs. Signed-off-by:
Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by:
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Laxman Dewangan authored
Maxim Semiconductor's PMIC MAX77620/MAX20024 has 8 GPIO pins which act as GPIO as well as special function mode. Add DT binding document to configure pins in function mode as well as pin configuration parameters. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Laxman Dewangan authored
Remove the use of parked_reg and use parked_bit for to know whether field is supported or not. This is fix for the patch commit 1d18a3f0 "pinctrl: tegra: avoid parked_reg and parked_bank Signed-off-by:
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Linus Walleij authored
This reverts commit 0d535833.
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Neil Armstrong authored
Add pinctrl and gpio DT bindings for Oxford Semiconductor OXNAS SoC Family. This version supports the ARM926EJ-S based OX810SE SoC with 34 IO pins. Signed-off-by:
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Neil Armstrong authored
Add pinctrl and gpio control support to Oxford Semiconductor OXNAS SoC Family. This version supports the ARM926EJ-S based OX810SE SoC with 34 IO pins. Signed-off-by:
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- 29 May, 2016 1 commit
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Linus Torvalds authored
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