- 17 Apr, 2024 31 commits
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Ma Jun authored
Waiting for system ready to fix the discovery initialization failure issue. This failure usually occurs when dGPU is removed and then rescanned via command line. It's caused by following two errors: [1] vram size is 0 [2] wrong binary signature Signed-off-by:
Ma Jun <Jun.Ma2@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Christian König authored
When we removed the hacky start code check we actually didn't took into account that *all* VRAM pages needs to be CPU accessible. Clean up the code and unify the handling into a single helper which checks if the whole resource is CPU accessible. The only place where a partial check would make sense is during eviction, but that is neglitible. Signed-off-by:
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xinhui pan authored
Verify the parameters of amdgpu_vm_bo_(map/replace_map/clearing_mappings) in one common place. Fixes: dc54d3d1 ("drm/amdgpu: implement AMDGPU_VA_OP_CLEAR v2") Cc: stable@vger.kernel.org Reported-by:
Vlad Stolyarov <hexed@google.com> Suggested-by:
xinhui pan <xinhui.pan@amd.com> Reviewed-by:
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Yang Wang authored
add new aca smu callback parse_error_code{} to avoid specific asic check in amdgpu_aca.c file Signed-off-by:Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Aric Cyr authored
This version brings along following fixes: * Expand dmub_cmd operations. * Update DVI configuration. * Modify power sequence. * Enable Z10 flag for IPS. * Multiple code cleanups. Acked-by:
Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
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Leo Li <sunpeng.li@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
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Rodrigo Siqueira authored
Add some missing registers expansion in the dcn201_link_encoder file. Reviewed-by:
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Rodrigo Siqueira authored
Fill ring buffer before offload. Reviewed-by:
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Rodrigo Siqueira authored
This commit remove some unused code and also rename one of the define. Reviewed-by:
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Eric Bernstein authored
[Why] Update FMT_CONTROL settings based on HW spec [How] Update FMT settings for 4:2:0 Reviewed-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
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Jonathan Kim authored
MES internally has a timeout allowance of 2 seconds. Increase driver timeout to 3 seconds to be safe. Signed-off-by:
Jonathan Kim <Jonathan.Kim@amd.com> Reviewed-by:
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Rodrigo Siqueira authored
This commit groups many parts of the code that are redundant or not used and drops all of them. Reviewed-by:
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Rodrigo Siqueira authored
This commit updates some comments to be more precise and adds another small comment to some other parts to improve the code readability. Reviewed-by:
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Rodrigo Siqueira authored
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Rodrigo Siqueira authored
Move the scl_data.format to be close to other similar parts. Reviewed-by:
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Mikita Lipski authored
[why] Driver was passing a wrong command version which to DMCUB which caused the DMCUB to treat it as 0, so it wouldn't support dual eDP and would override the panel index to 0 instead of choosing between 0/1. [how] Use DMUB_CMD_PSR_CONTROL_VERSION_1 instead of PSR_VERSION_1. Reviewed-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
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Ethan Bitnun authored
The previous assumption that there will be an optimize_bandwidth call following every prepare_bandwidth call was incorrect and caused small inaccuracies in logging, as some info was only updated in later prepare calls. Reviewed-by:
Ethan Bitnun <Ethan.Bitnun@amd.com> Reviewed-by:
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Rodrigo Siqueira authored
Update headers by removing two unecessary headers and include a new one. Reviewed-by:
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Rodrigo Siqueira authored
The chip ID DEVICE_ID_NV_13FE is not meaningful and represents a legacy way of dealing with chip ID. This commit uses dc_version instead of chip_id and also DCN_VERSION_2_01 instead of DEVICE_ID_NV_13FE. Signed-off-by:
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Alex Deucher authored
This reverts commit b5abd7f9. This change breaks DSC on 4k monitors at 144Hz over USB-C. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3254Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Anthony Koo authored
Update dmub_cmd to manipulate SDP control in replay FSM, add command for panel_cntl, expand link rate enum, and increase the reserve byte. Acked-by:
Anthony Koo <anthony.koo@amd.com> Tested-by:
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Sunil Khatri authored
Add vbios version in the devcoredump along with formatting the information with proper alignment. Reviewed-by:
Sunil Khatri <sunil.khatri@amd.com> Signed-off-by:
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Alex Deucher authored
Need to take the srbm_mutex and while we are here, use the helper function soc21_grbm_select(); Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Sung Joon Kim authored
Rework part of the modifications made to the power sequence and resource allocation logic. Reviewed-by:
Xi (Alex) Liu <xi.liu@amd.com> Acked-by:
Sung Joon Kim <sungjoon.kim@amd.com> Tested-by:
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Sung Joon Kim authored
[why] IPS FSM requires Z10 flag to be enabled to do save and restore the registers properly. [how] Enable Z10 and use the correct function to determine Z10 capability Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by:
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Chaitanya Dhere authored
[Why] Pointer initialization and assignment for dml2_options is not done correctly. While this works for some compilers, others give an error. [How] Modify dc_state_create code to correctly initialize the dml2_opt pointer and pass it to dml2_create. Also update the code with correct derefrence operations. Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by:
Chaitanya Dhere <chaitanya.dhere@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why] IPS ono sequence ordering differs based on the ASIC. [How] Detect the ASIC ID revision and set the boot option accordingly. Feed it through the DCN35 DMUB functions. Reviewed-by:
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Samson Tam authored
[Why] Adding support for chroma subsampling offset (cositing) in scaler calculations to adjust reference point where we determine post-scaling chroma value in YUV420 surfaces. [How] Add support for cositing options: NONE, LEFT and TOPLEFT Add debug option force_cositing and set default to TOPLEFT to maintain same behaviour as without offset support. Reviewed-by:
Jun Lei <jun.lei@amd.com> Acked-by:
Samson Tam <samson.tam@amd.com> Tested-by:
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Charlene Liu authored
Limit the code change for ips enable to reduce the impact for now. Also exit_ips first before dc_power_down to avoid 0x9f. Reviewed-by:
Chris Park <chris.park@amd.com> Acked-by:
Charlene Liu <charlene.liu@amd.com> Tested-by:
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Sung Joon Kim authored
To reduce the complexity of pipe resource allocation for different use-cases, now we search for any free pipe sequentially rather than from bottom up. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
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- 12 Apr, 2024 9 commits
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Chris Park authored
[Why] DVI is TMDS signal like HDMI but without audio. Current signal check does not correctly reflect DVI clock programming. [How] Define a new signal check for TMDS that includes DVI to HDMI TMDS programming. Reviewed-by:
Dillon Varone <dillon.varone@amd.com> Acked-by:
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Sung Joon Kim authored
Need to update the power sequence to help prevent potential issues like multi-display or multi-plane. Reviewed-by:
Duncan Ma <duncan.ma@amd.com> Acked-by:
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Aric Cyr authored
This version brings along the following: - DCN10 fixes - DCN316 fixes - DML2 fixes - DWB fixes - Expanded FAMS support - Misc code style fixes - ODM fixes - VSC SDP fixes Acked-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
This commit makes some small adjustments in the dwb header. Acked-by:
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Felix Kuehling authored
Fix memory leak due to a leaked mmget reference on an error handling code path that is triggered when attempting to create KFD processes while a GPU reset is in progress. Fixes: 0ab2d753 ("drm/amdkfd: prepare per-process debug enable and disable") CC: Xiaogang Chen <xiaogang.chen@amd.com> Signed-off-by:
Felix Kuehling <felix.kuehling@amd.com> Tested-by:
Harish Kasiviswanthan <Harish.Kasiviswanthan@amd.com> Reviewed-by:
Mukul Joshi <mukul.joshi@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
Change DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT with DP_PHY_REPEATER_128B132B_RATES. Acked-by:
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Rodrigo Siqueira authored
Set OTG/OPTC parameters to 0 if something goes wrong on DCN10. Acked-by:
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Rodrigo Siqueira authored
Set OTG/OPTC parameter to 0 if failed to set DRR. Acked-by:
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Rodrigo Siqueira authored
Update DCN10 to use legacy fast update and ensure that the MPCC count is the same as the pipe_count. Acked-by:
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