- 07 Nov, 2022 33 commits
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Johan Hovold authored
The QMP pipe clock is used by the USB part of the PHY so drop the corresponding properties from the DP child node. Fixes: 23737b95 ("arm64: dts: qcom: sm6350: Add USB1 nodes") Signed-off-by:
Johan Hovold <johan+linaro@kernel.org> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221026152511.9661-3-johan+linaro@kernel.org
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Johan Hovold authored
The QMP pipe clock is used by the USB part of the PHY so drop the corresponding properties from the DP child node. Fixes: 5aa0d1be ("arm64: dts: qcom: sm8250: switch usb1 qmp phy to USB3+DP mode") Signed-off-by:
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Manivannan Sadhasivam authored
Add thermal zone support by making use of the thermistor SYS_THERM6. Based on experiments, this thermistor seems to reflect the actual surface temperature of the laptop. For the cooling device, all BIG CPU cores are throttled down to keep the temperature at a sane level. Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by:
Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by:
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Manivannan Sadhasivam authored
Add ADC_TM5 channels of PM8280_{1/2} for monitoring the temperature from external thermistors connected to AMUX pins. The temperature measurements are collected from the PMK8280's VADC channels that expose the measurements from secondary PMICs PM8280_{1/2}. Reviewed-by:Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
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Manivannan Sadhasivam authored
Add VADC channel of PMR735A for measuring the on-chip die temperature. Reviewed-by:
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Manivannan Sadhasivam authored
Add VADC channels of PM8280_{1/2} PMICs for measuring the on-chip die temperature and external thermistors connected to the AMUX pins. The measurements are collected by the primary PMIC PMK8280 from the secondary PMICs PM8280_{1/2} and exposed over the PMK8280's VADC channels. Reviewed-by: -
Manivannan Sadhasivam authored
Add VADC channels for measuring the on-chip die temperature and external crystal osciallator temperature of PMK8280. Reviewed-by:
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Manivannan Sadhasivam authored
Enable resetting the PMK8280 through RESIN block in SC8280XP X13s. Reviewed-by:
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Manivannan Sadhasivam authored
Thermal Monitoring block ADC5 (TM5) in PMK8280 can be used to monitor the temperature from secondary PMICs like PM8280. Reviewed-by:
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Manivannan Sadhasivam authored
Add support for ADC7 block available in PMK8280 for reading the temperature via the AMUX pins. Reviewed-by:
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Manivannan Sadhasivam authored
The RESIN input can be used to reset the PMK8280 PMIC. Enabling the RESIN block allows the PMK8280 to detect reset input via RESIN_N pin. Reviewed-by:
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Manivannan Sadhasivam authored
Add thermal zones for the PM8280_{1/2} PMICs by using the temperature alarm blocks as the thermal sensors. Temperature trip points are inherited from PM8350 PMIC. Reviewed-by: -
Manivannan Sadhasivam authored
Add support for temperature alarm feature in the PM8280_{1/2} PMICs. Reviewed-by: -
Manivannan Sadhasivam authored
As per the new ADC7 architecture used by the Qualcomm PMICs, each PMIC has the static Slave ID (SID) assigned by default. The primary PMIC PMK8350 is responsible for collecting the temperature/voltage data from the slave PMICs and exposing them via it's registers. For getting the measurements from the slave PMICs, PMK8350 uses the channel ID encoded with the SID of the relevant PMIC. So far, the dt-binding for the slave PMIC PM8350 assumed that there will be only one PM8350 in a system. So it harcoded SID 1 with channel IDs. But this got changed in platforms such as Lenovo X13s where there are a couple of PM8350 PMICs available. So to address multiple PM8350s, change the binding to accept the SID specified by the user and use it for encoding the channel ID. It should be noted that, even though the SID is static it is not globally unique. Only the primary PMIC has the unique SID id 0. Reviewed-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Dmitry Baryshkov authored
The 'qcom,dsi-ctrl-6g-qcm2290' compatibility string was added in the commit ee1f0967 ("drm/msm/dsi: Add support for qcm2290 dsi controller") in February 2022, but was not properly documented in the bindings. Adding this compatibility string to display/msm/dsi-controller-main.yaml caused a warning from qcom-soc.yaml. Fix the warning by adding an exception to the mentioned file. Signed-off-by:
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Vincent Knecht authored
Add si-en,sn3190 LED controller to enable white LED indicator. This requires adding the additional "enable" gpio that the OEM choose to use, despite it not being mentioned in si-en,sn3190 datasheet nor supported by the driver. Signed-off-by:
Vincent Knecht <vincent.knecht@mailoo.org> Reviewed-by:
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Vincent Knecht authored
Add support for torch LED on GPIO 32. Signed-off-by:
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Dmitry Torokhov authored
The driver for the codec, when resetting the chip, first drives the line low, and then high. This means that the line is active low. Change the annotation in the DTS accordingly. Fixes: f8b4eb64 ("arm64: dts: qcom: sc7280: Add wcd9385 codec node for CRD 1.0/2.0 and IDP boards") Signed-off-by:
Dmitry Torokhov <dmitry.torokhov@gmail.com> Signed-off-by:
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Dmitry Torokhov authored
The driver for the codec, when resetting the chip, first drives the line low, and then high. This means that the line is active low. Change the annotation in the DTS accordingly. Fixes: 0a3a56a9 ("arm64: dts: qcom: sc7280: Add wcd9385 codec node for CRD 3.0/3.1") Signed-off-by:
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Dmitry Torokhov authored
The driver for the codec, when resetting the chip, first drives the line low, and then high. This means that the line is active low. Change the annotation in the DTS accordingly. Fixes: 36c9d012 ("arm64: dts: qcom: use GPIO flags for tlmm") Fixes: 5a263cf6 ("arm64: dts: qcom: sm8250-mtp: Add wcd9380 audio codec node") Signed-off-by:
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Dmitry Torokhov authored
When resetting the block, the reset line is being driven low and then high, which means that the line in DTS should be annotated as "active low". It will become important when wcd9335 driver will be converted to gpiod API that respects declared line polarities. Fixes: f3eb39a5 ("arm64: dts: db820c: Add sound card support") Signed-off-by:
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Krzysztof Kozlowski authored
Based on downstream DTS, it seems that SM8450 QRD has microSD card slot. Signed-off-by:
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Krzysztof Kozlowski authored
The HDK8450 has microSD card slot. Signed-off-by:
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Krzysztof Kozlowski authored
SDHCI on SM8450 HDK also has problems with SDR104/SDR50: mmc0: card never left busy state mmc0: error -110 whilst initialising SD card so I think it is safe to assume this issue affects all SM8450 boards. Move the quirk disallowing these modes to the SoC DTSI, to spare people working on other boards the misery of debugging this issue. Signed-off-by:
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Krzysztof Kozlowski authored
The SDHCI pin configuration/mux nodes are actually common to all upstreamed boards, so define them in SoC DTSI to reduce code duplication. Signed-off-by:
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Johan Hovold authored
The sizes of the UFS PHY register regions are too small and does specifically not cover all registers used by the Linux driver. As Linux maps these regions as full pages this is currently not an issue on Linux, but let's update the sizes to match the vendor driver. Fixes: 07fa917a ("arm64: dts: qcom: sm8450: add ufs nodes") Signed-off-by:
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Johan Hovold authored
The sizes of the UFS PHY register regions are too small and does specifically not cover all registers used by the Linux driver. As Linux maps these regions as full pages this is currently not an issue on Linux, but let's update the sizes to match the vendor driver. Fixes: 59c7cf81 ("arm64: dts: qcom: sm8350: Add UFS nodes") Signed-off-by:
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Johan Hovold authored
The sizes of the UFS PHY register regions are too small and does specifically not cover all registers used by the Linux driver. As Linux maps these regions as full pages this is currently not an issue on Linux, but let's update the sizes to match the vendor driver. Fixes: b7e2fba0 ("arm64: dts: qcom: sm8250: Add UFS controller and PHY") Signed-off-by:
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Johan Hovold authored
The sizes of the UFS PHY register regions are too small and does specifically not cover all registers used by the Linux driver. As Linux maps these regions as full pages this is currently not an issue on Linux, but let's update the sizes to match the vendor driver. Fixes: 3834a2e9 ("arm64: dts: qcom: sm8150: Add ufs nodes") Signed-off-by:
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Krzysztof Kozlowski authored
DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by:
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Harry Austen authored
Add initial support for OnePlus 3 and 3T mobile phones. They are based on the MSM8996 SoC. Co-developed-by:
Yassine Oudjana <y.oudjana@protonmail.com> Signed-off-by:
Harry Austen <hpausten@protonmail.com> Signed-off-by:
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Harry Austen authored
Add compatible strings for the OnePlus 3 and 3T phones which utilise the Qualcomm MSM8996 SoC. Signed-off-by:
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Harry Austen authored
Add support for the sixth I2C interface on the MSM8996 SoC. Signed-off-by:
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- 06 Nov, 2022 7 commits
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Harry Austen authored
Use one-based indexing throughout the file for BLSP devices to avoid confusion. Most of the node names and labels are consistent already. This patch just fixes a few pinconf node names to match the one-based indexing used in the label names. Signed-off-by:
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Krzysztof Kozlowski authored
DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Signed-off-by:
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Krzysztof Kozlowski authored
Pin configuration has no "input-high" property, so drop it from node described as Wifi host wake up pin. Signed-off-by:
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Krzysztof Kozlowski authored
DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Merge subnodes named 'pinconf' and 'pinmux' into one entry, add function where missing (required by bindings for GPIOs) and reorganize overriding pins by boards. Split the SPI and UART configuration into separate nodes 1. SPI (MOSI, MISO, SCLK), SPI chip-select, SPI chip-select via GPIO, 2. UART per each pin: TX, RX and optional CTS/RTS. This allows each board to customize them easily without adding any new nodes. Signed-off-by:
Douglas Anderson <dianders@chromium.org> Tested-by:
Stephen Boyd <swboyd@chromium.org> Signed-off-by:
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Krzysztof Kozlowski authored
arm64: dts: qcom: sc7180: revert "arm64: dts: qcom: sc7180: Avoid glitching SPI CS at bootup on trogdor" This reverts commit e440e30e because it is not a reliable way of fixing SPI CS glitch and it depends on specific Linux kernel pin controller driver behavior. This behavior of kernel driver was changed in commit b991f8c3 ("pinctrl: core: Handling pinmux and pinconf separately") thus effectively the DTS fix stopped being effective. Proper solution for the glitching SPI chip select must be implemented in the drivers, not via ordering of entries in DTS, and is already introduced in commit d21f4b7f ("pinctrl: qcom: Avoid glitching lines when we first mux to output"). Signed-off-by:
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Krzysztof Kozlowski authored
The Trogdor Homestar DTSI adds additional GPIO52 pin to secondary I2S pins ("sec_mi2s_active") and configures it to "mi2s_1" function. The Trogdor DTSI (which is included by Homestar) configures drive strength and bias for all "sec_mi2s_active" pins, thus the intention was to apply this configuration also to GPIO52 on Homestar. Reported-by: -
Krzysztof Kozlowski authored
Use SM6350 as fallback for GPI DMA, to indicate devices are compatible and that drivers can bind with only one compatible. Signed-off-by:
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