- 03 Apr, 2023 23 commits
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Imre Deak authored
Move blocking/unblocking the TC-cold power state to the platform specific PHY connect / disconnect hooks. This allows for adjusting the connect/disconnect sequence as required for each platform. Reviewed-by:
Mika Kahola <mika.kahola@intel.com> Signed-off-by:
Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230323142035.1432621-17-imre.deak@intel.com
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Imre Deak authored
After the previous patch the TC mode in the connect/disconnect functions is always in sync with the VBT legacy port flag, so for consistency with the rest of the function check the TC mode instead of the VBT flag. Reviewed-by:
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Imre Deak authored
A follow-up patch simplifies the tc_cold_block()/unblock() functions, dropping the power domain parameter. For this it must be ensured that the power domain - which depends on the actual TC mode and so the VBT legacy port flag - can't change while the PHY is in a connected state and accordingly TC-cold is blocked. Make this so, by fixing up the VBT legacy flag only in the disconnected TC mode, instead of whenever the HPD state is retrieved. Reviewed-by:
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Imre Deak authored
Add TC PHY hooks to connect/disconnect the PHY. A follow-up patch will add the ADLP specific hooks for these. Reviewed-by:
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Imre Deak authored
Factor out a function verifying the PHY connected state in legacy or DP-alt mode. This is common to all platforms, which can be reused in platform specific connect hooks added in follow-up patches. No functional changes. Reviewed-by:
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Imre Deak authored
Add generic handlers to connect/disconnect a PHY. Setting the TC mode to the target mode deducted from the HPD state and - if connecting to this mode fails - falling back to connecting to the default (TBT) mode are common to all platforms; move the logic for this from the ICL specific connect / disconnect handlers to the generic ones. Reviewed-by:
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Imre Deak authored
Add a TC PHY hook to read out the PHY HW state on each platform, move the common parts to the generic helper. Reviewed-by:
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Imre Deak authored
Add TC PHY hooks to get the PHY ready/owned state on each platform, replacing the corresponding if ladder. Reviewed-by:
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Imre Deak authored
Add a table of TC PHY hooks which can be used to call platform specific TC PHY handlers, replacing the corresponding if ladders. Add the hook to retrieve the PHY's HPD live status. Move the common part fixing up the VBT legacy port flag to the generic helper. Reviewed-by:
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Imre Deak authored
Move the intel_tc_port struct to intel_tc.c for better isolation. This requires allocating the struct dynamically. Reviewed-by:
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Imre Deak authored
Check explicitly if the port passed to intel_tc_port_fia_max_lane_count() has a TC PHY, instead of relying on the default TC mode value set for non-TC PHY ports. Reviewed-by:
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Imre Deak authored
Move the TC port specific fields from intel_digital_port to a new intel_tc_port struct. Pass an intel_tc_port pointer to all static functions in intel_tc.c keeping dig_port accessible for these via a pointer stored in the new struct. The next patch will allocate the intel_tc_port dynamically, allowing moving the struct definition to intel_tc.c. Reviewed-by:
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Imre Deak authored
For consistency use the tc_phy prefix for all TC PHY functions. Reviewed-by:
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Imre Deak authored
For consistency rename tc_phy_status_complete() to tc_phy_is_ready() following the terminology of new platforms. Reviewed-by:
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Imre Deak authored
Use the usual adlp prefix for all ADLP specific TC PHY functions. Other ADL platforms don't support TC. Reviewed-by:
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Imre Deak authored
Arrange the TC PHY HW state setup/query functions into platform specific and generic groups. This prepares for upcoming patches adding generic TC PHY handlers and platform specific hooks for these, replacing the corresponding if ladders. No functional changes. v2: Fix non kernel-doc multiline comments. (Jani) Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by:
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Swati Sharma authored
DSC_Output_Format_Sink_Support entry is added to i915_dsc_fec_support_show to depict if sink supports DSC output formats (RGB/YCbCr420/YCbCr444). Also, new debugfs entry is created to enforce output format. This is required because of our driver policy. For ex. if a mode is supported in both RGB and YCbCr420 output formats by the sink, our policy is to try RGB first and fall back to YCbCr420, if mode cannot be shown using RGB. So, to test other output formats like YCbCr420 or YCbCr444, we need a debugfs entry (force_dsc_output_format) to force this output format. v2: -Func name changed to intel_output_format_name() (Jani N) -Return forced o/p format from intel_dp_output_format() (Jani N) v3: -output_format_str[] to remain static (Jani N) Signed-off-by:Swati Sharma <swati2.sharma@intel.com> Reviewed-by:
Uma Shankar <uma.shankar@intel.com> Signed-off-by:
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Suraj Kandpal authored
Add function to check if slice design requirements are being met as defined in Bspec: 49259 in the section Slice Design Requirement --v7 -remove full bspec link [Jani] -rename intel_dsc_check_slice_design_req to intel_dsc_slice_dimensions_valid [Jani] --v8 -fix condition to check if slice width and height are of two -fix minimum pixel in slice condition --v10 -condition should be < rather then >= [Uma] Cc: Uma Shankar <uma.shankar@intel.com> Signed-off-by:
Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by:
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Suraj Kandpal authored
Now that we have laid the groundwork for YUV420 Enablement we fill up native_420 field in vdsc_cfg and add appropriate checks wherever required. ---v2 -adding native_422 field as 0 [Vandita] -filling in second_line_bpg_offset, second_line_offset_adj and nsl_bpg_offset in vds_cfg when native_420 is true ---v3 -adding display version check to solve igt issue --v7 -remove is_pipe_dsc check as its always true for D14 [Jani] --v10 -keep sink capability check [Jani] -move from !(x == y || w == z) to x !=y && w != z [Jani] --v11 -avoid native_420 computation if not gen14 [Uma] --v12 -fix state mismatch issue of compressed_bpp Cc: Uma Shankar <uma.shankar@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by:
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Suraj Kandpal authored
Implementation of VDSC for YCbCr420. Add QP tables for 8,10,12 BPC from rc_tables.h in intel_qp_tables.c (Derived from C-Model, which is given along with DSC1.2a Spec from Vesa) intel_lookup_range_min/max_qp functons need to take into account the output format. Based on that appropriate qp table need to be chosen. Other rc_parameters need to be set where currently values for 444 format is hardcoded in calculate_rc_parameters( ). vdsc_cfg struct needs to be filled with output format information, where these are hardcoded for 444 format. Bspec: 49259 Signed-off-by:
Vandita Kulkarni <Vandita.kulkarni@intel.com> Reviewed-by:
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Suraj Kandpal authored
Adding new DSC register which are introducted MTL onwards Signed-off-by:
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Ankit Nautiyal authored
Go with DSC only if the given output_format is supported. v2: Use drm helper to get DSC format support for sink. v3: remove drm_dp_dsc_compute_bpp. Cc: Uma Shankar <uma.shankar@intel.com> Signed-off-by:
Ankit Nautiyal <ankit.k.nautiyal@intel.com> Reviewed-by:
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Ankit Nautiyal authored
Add helper to check if the DP sink supports DSC with the given o/p format. v2: Add documentation for the helper. (Uma Shankar) v3: /** instead of /* (Uma Shankar) Signed-off-by:
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- 31 Mar, 2023 9 commits
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Ville Syrjälä authored
Define CUR_CHICKEN so we don't have to remember the offset. Looks like it's getting introduced in mtl. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230329190445.13456-3-ville.syrjala@linux.intel.comReviewed-by:
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Ville Syrjälä authored
Add tgl+ comments to the PLANE_CHICKEN registers which I apparently forgot to add when defining the registers. Signed-off-by:
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Ville Syrjälä authored
Cursor is not a universal plane and thus doesn't have the PLANE_CHICKEN register. Skip it. Fixes: c5de2484 ("drm/i915/dpt: Add a modparam to disable DPT via the chicken bit") Signed-off-by:
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Jouni Högander authored
Implement Display WA #1136 for Pre-ICL. Bspec: 21664 v2: Handle disable psr in pre/post plane hooks Signed-off-by:
Jouni Högander <jouni.hogander@intel.com> Reviewed-by:
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Jouni Högander authored
Ensure vblank >= psr2 vblank where Psr2 vblank = PSR2_CTL Block Count Number maximum line count. Bspec: 71580, 49274 v2: Use calculated block count number maximum line count Signed-off-by:
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Jouni Högander authored
Add helpers to make it more clear how PSR2_CTL[Block Count Number] is configured. Signed-off-by:
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Jouni Högander authored
PSR WM optimization should be disabled based on any wm level being disabled. Also same WA should be applied for ICL as well. Bspec: 71580 v5: - Set in pre plane hook and clear in post plane hook v4: - Handle mode change in psr enable/disable - Handle wm_level_disable changes separately in pre plane hook v3: - Split patch v2: - set/clear chicken bit in post_plane_update - apply for ICL as well Signed-off-by:
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Jouni Högander authored
Wa_16013835468 is a separate from Wa_14015648006 and needs to be applied for display version 12. Fix this by removing all the references to Wa_14015648006 and apply Wa_16013835468 according to Bspec. Also move workaround into separate function as a preparation for Wa_14015648006 implementation. Bspec: 55378 v3: - apply for display version 12 only v2: - keep applying the wa in intel_psr_enable_source Signed-off-by:
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Jouni Högander authored
pre/post hooks are doing things differently. Unify them. Signed-off-by:
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- 30 Mar, 2023 7 commits
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Daniele Ceraolo Spurio authored
The PTEs expect the offset from the base of the fake LMEM region (i.e. the base of stolen) and not from the base of the DSM. Quoting the specs: "Driver will set the Device Memory bit = 1 in the PTE when pointing to a page in DSM and program the PTE with offset from LMEM_BAR. Device Memory Offset from LMEM_BAR is same as offset from BGSM." DSM starts 8MBs from BGSM, so we set dsm_base = 8MB. Signed-off-by:
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Nirmoy Das <nirmoy.das@intel.com> Cc: Fei Yang <fei.yang@intel.com> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by:
Andi Shyti <andi.shyti@linux.intel.com> Reviewed-by:
Nirmoy Das <nirmoy.das@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230328012430.2524330-1-daniele.ceraolospurio@intel.com
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Jani Nikula authored
Clean up i915_reg.h by splitting out DSB regs to display/intel_dsb_regs.h. Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Reviewed-by:
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Jani Nikula authored
Clean up i915_reg.h by splitting out FDI regs to display/intel_fdi_regs.h. Signed-off-by:
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Jani Nikula authored
Clean up i915_reg.h by splitting out DP AUX regs to display/intel_dp_aux_regs.h. Signed-off-by:
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Jani Nikula authored
Clean up i915_reg.h by splitting out TV regs to display/intel_tv_regs.h. Signed-off-by:
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Jani Nikula authored
Clean up i915_reg.h by splitting out PPS regs to display/intel_pps_regs.h. Signed-off-by:
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Ville Syrjälä authored
Only the PWM output mode of the utility pin is incompatible with DC6/LCPLL disable. Check for that specifically. References: https://gitlab.freedesktop.org/drm/intel/-/issues/6609Signed-off-by:
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- 29 Mar, 2023 1 commit
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Stanislav Lisovskiy authored
For obvious reasons, we use compressed bpp instead of pipe bpp for DSC DP SST case. Lets be consistent and use compressed bpp instead of pipe bpp, also in DP MST DSC case. Signed-off-by:
Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Reviewed-by:
Vinod Govindapillai <vinod.govindapillai@intel.com> Fixes: d51f25eb ("drm/i915: Add DSC support to MST path") Link: https://patchwork.freedesktop.org/patch/msgid/20230327064217.24033-1-stanislav.lisovskiy@intel.com
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