- 24 Jan, 2014 35 commits
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Hauke Mehrtens authored
With this patch we prevent the irq from being fired when it is registered. The Hardware fires an IRQ when input signal XOR polarity AND gpio mask is 1. Now we are setting polarity to a vlaue so that is is 0 when we register it. In addition we also set the irq mask register to 0 when the irq handler is initialized, so all gpio irqs are masked and there will be no unexpected irq. Signed-off-by:
Hauke Mehrtens <hauke@hauke-m.de> Tested-by:
Rafał Miłecki <zajec5@gmail.com> Signed-off-by:
John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6304/
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Markos Chandras authored
BUG() can be a noop if CONFIG_BUG is not selected, leading to the following build problem on a randconfig: arch/mips/bcm63xx/cpu.c: In function 'detect_cpu_clock': arch/mips/bcm63xx/cpu.c:254:1: error: control reaches end of non-void function [-Werror=return-type] We fix this problem by replacing BUG() with panic() since it's best to handle the case of an unknown board instead of silently returning a random clock frequency. Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com> Acked-by:
Steven J. Hill <Steven.Hill@imgtec.com> Acked-by:
Jonas Gorski <jogo@openwrt.org> Signed-off-by:
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Rafał Miłecki authored
This old wgt634u.c was trying to implement a bit ugly support for Netgear WGT634U. It provided info about LED, flash mapping & layout and was trying to handle reset button. This is not needed anymore as we have replacement for all this stuff. Signed-off-by:
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Rafał Miłecki authored
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Rafał Miłecki authored
This includes all devices from OpenWrt's "diag" that we support in arch code (we have entries for in enum bcm47xx_board). Signed-off-by:
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Rafał Miłecki authored
So far this adds support for one Netgear model only, but it's designed and ready to add many more device. We could hopefully import database from OpenWrt. Support for SSB is currently disabled, because SSB doesn't implement IRQ domain yet. Signed-off-by:
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Rafał Miłecki authored
So far this is mostly just a proof of concept, database consists of a single device. Creating a nice iterateable array wasn't an option because devices have different amount of LEDs. And we don't want to waste memory just because of support for a device with dozens on LEDs. Signed-off-by:
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Hauke Mehrtens authored
The BCM4706 has a problem with the CPU wait instruction. When r4k_wait or r4k_wait_irqoff is used will just hang and not return from a msleep(). Removing the cpu_wait functionality is a workaround for this problem. The BCM4716 does not have this problem. The BCM4706 SoC uses a MIPS 74K V4.9 CPU. Signed-off-by:
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Hauke Mehrtens authored
This will add the board name to the machine entry in /proc/cpuinfo. Signed-off-by:
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Jayachandran C authored
Move wakeup to after early console. This will allow us to display error messages when cores are not woken up. Also reduce the wait time for core to come up. Signed-off-by:
Jayachandran C <jchandra@broadcom.com> Signed-off-by:
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Jayachandran C authored
The early serial code is not needed because we already have early printk support provided by common/earlycons.c This change also fixes the following build error that occurs when CONFIG_SERIAL_8250 is not configured for Netlogic XLR boards: arch/mips/built-in.o: In function `nlm_early_serial_setup': setup.c:(.init.text+0x274): undefined reference to `early_serial_setup' make: *** [vmlinux] Error 1 Reported-by:
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Jayachandran C authored
Add a default device tree fie for XLP9XX boards, and add code to use this device tree if no DTB is passed to the kernel. Signed-off-by:
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Jayachandran C authored
Support for adding legacy IRQ domain for XLP9XX. The node id of the PIC has to be calulated differently for XLP9XX. Signed-off-by:
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Ganesan Ramalingam authored
XLP9XX has a USB 3.0 controller on-chip with 2 xHCI ports. The USB block is similar to the one on XLP2XX, so update usb-init-xlp2.c to handle XLP9XX as well. Signed-off-by:
Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by:
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Jayachandran C authored
Add PCI support for Netlogic XLP9XX. The PCI registers and SoC bus numbers have changed in XLP9XX. Also skip a few (bus,dev,fn) combinations which have issues when read. Signed-off-by:
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Jayachandran C authored
XLP9XX has 20 cores per node, opposed to 8 on earlier XLP8XX. Update code that calculates node id from cpu id to handle this. Signed-off-by:
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Jayachandran C authored
Update bridge code. Add code to the XLP9XX registers for DRAM size, limit and node when running on XLPXX Signed-off-by:
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Jayachandran C authored
Update IO offset of the early console UART. Signed-off-by:
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Jayachandran C authored
Add the SYS block registers for XLP9XX, most of them have changed. The wakeup sequence has been updated to set the coherent mode from the main thread rather than the woken up thread. Signed-off-by:
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Jayachandran C authored
Functions for the XLP9XX interrupt table entry format and other PIC register changes. Signed-off-by:
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Jayachandran C authored
Most IO block offsets have changed in XLP9XX. Update iomap.h to add the new addresses of different SoC blocks like PIC, SYS, UART etc. that are needed by the base code. On XLP9xx, the SoC blocks of other nodes are seen on a PCI bus corresponding to the node. Update iomap code to reflect this. Signed-off-by:
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Jayachandran C authored
Adds processor ID of XLP 9XX to asm/cpu.h. Update netlogic/xlp-hal/xlp.h to add cpu_is_xlp9xx() and to update cpu_is_xlpii() to support XLP 9XX. Signed-off-by:
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Jayachandran C authored
Use the FUSE register to get the list of active cores in the CPU instead of using the CPU reset register, this is the recommended method. Also add code to mask the coremask with the default number of cores for each processor series. Signed-off-by:
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Jayachandran C authored
Add macro nlm_node_present() that can be used to check if a node is present in a multi-chip configuration. This can be used even when NUMA is not enabled. Signed-off-by:
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Yonghong Song authored
On XLPII CPUs, the L1D cache has to be flushed with regular cache operations before enabling threads in a core. Signed-off-by:
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Jayachandran C authored
No change in logic, the changes are: * cleanup some whitespace and comments * remove confusing argument of SYS_CPU_COHERENT_BASE macro * make the numerical labels in macros consistent Signed-off-by:
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Jayachandran C authored
Add mach-netlogic/topology.h which contains XLP cpu number to core and node mapping. Signed-off-by:
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Jayachandran C authored
Add MSI chip and MSIX chip definitions. For MSI, we map the link interrupt to a MSI link IRQ which will do a second level of dispatch based on the MSI status register. The MSI chip definitions use the MSI enable register to enable and disable the MSI irqs. For MSI-X, we split the 32 available MSI-X vectors across the four PCIe links (8 each). These PIC interrupts generate an IRQ per link which uses a second level dispatch as well. The MSI-X chip definition uses the standard functions to enable and disable interrupts. Signed-off-by:
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Deng-Cheng Zhu authored
Boot log says: pci 0000:00:0a.3: no compatible bridge window for [io 0x1000-0x103f] pci 0000:00:0a.3: no compatible bridge window for [io 0x1100-0x110f] The io resource starting point on Malta was modified by c5de50da (MIPS: Malta: Change start address to avoid conflicts.) to avoid conflicts with ACPI and SMB devices. In fact, that was not needed (and now causing southbridge ACPI missing) since 166c6370 (PCI: add pci_create_root_bus() that accepts resource list) and 7c090e5b (mips/PCI: convert to pci_scan_root_bus() for correct root bus resources) had already done the correct fix. This patch actually reverts the change made by c5de50da. And with this fix, log says: pci 0000:00:0a.3: quirk: [io 0x1000-0x103f] claimed by PIIX4 ACPI pci 0000:00:0a.3: quirk: [io 0x1100-0x110f] claimed by PIIX4 SMB These things may not be used but as part of platform resources are better off to be included. Cc: Steven J. Hill <Steven.Hill@imgtec.com> Signed-off-by:
Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Signed-off-by:
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Aaro Koskinen authored
Currently the supported ISA is only printed on the latest architectures. Print it also on legacy platforms. Signed-off-by:
Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by:
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Apelete Seketeli authored
The platform data already available in tree for JZ4740 USB Device Controller was previously used by an out-of-tree USB gadget driver which was not relying on the musb driver and was written by Ingenic and the Qi-Hardware community. Update platform data for JZ4740 USB device controller to be used with musb driver. Signed-off-by:
Apelete Seketeli <apelete@seketeli.net> Acked-by:
Lars-Peter Clausen <lars@metafoo.de> Signed-off-by:
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Eunbong Song authored
This patch removes CONFIG_MTD_PARTITIONS in config files for MIPS. Because CONFIG_MTD_PARTITIONS was removed by commit 6a8a98b2. Signed-off-by:
Eunbong Song <eunb.song@samsung.com>
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Paul Burton authored
There is already an init_dsp function which checks cpu_has_dsp & calls __init_dsp if it does. Make use of it instead of duplicating the same code. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Reviewed-by:
Qais Yousef <qais.yousef@imgtec.com> Signed-off-by:
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Paul Burton authored
This patch cleans up the declaration of the resume function by replacing void pointers with their correct types. The irrelevant & incorrect comment preceeding the resume function is replaced by one documenting its function. Signed-off-by:
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Apelete Seketeli authored
Add defconfig for the Ben NanoNote handheld computer which is built around QI_LB60 board and Ingenic JZ4740 MIPS SoC. Signed-off-by:
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- 23 Jan, 2014 5 commits
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Rafał Miłecki authored
Input GPIO changes can generate interrupts, but we need kind of ACK for them by changing IRQ polarity. This is required to stop hardware from keep generating interrupts and generate another one on the next GPIO state change. This code allows using GPIOs with standard interrupts and add for example GPIO buttons support. Signed-off-by:
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Qais Yousef authored
The file uses u16 type but doesn't include its definition explicitly I was getting this error when including this header in my driver: arch/mips/include/asm/mipsregs.h:644:33: error: unknown type name ‘u16’ Signed-off-by:
David Daney <david.daney@cavium.com> Signed-off-by:
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Qais Yousef authored
we want the device tree to be unflattened into non init memory so it can be accessed later by, for example, a probing function of a driver module. Signed-off-by:
James Hogan <james.hogan@imgtec.com> Signed-off-by:
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Qais Yousef authored
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Qais Yousef authored
The defaults are not always applicable and it makes it hard for the bootloader to override them. By removing it we give the bootloader full control over what command line parameters to pass. Without this change we will need to modify the built-in dtb to add bootloader cmd line parameters or do some work to append them after we unflatten the device tree. Sead3 is a development board, that's why we want to be able to change boot parameters on the fly from the bootloader. Signed-off-by:
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