1. 19 Apr, 2022 2 commits
    • Michael Srba's avatar
      bus: add driver for initializing the SSC bus on (some) qcom SoCs · 97d485ed
      Michael Srba authored
      Add bindings for the AHB bus which exposes the SSC (Snapdragon Sensor Core)
      block in the global address space. This bus (and the SSC block itself) is
      present on certain qcom SoCs.
      
      In typical configuration, this bus (as some of the clocks and registers
      that we need to manipulate) is not accessible to Linux, and the resources
      on this bus are indirectly accessed by communicating with a hexagon CPU
      core residing in the SSC block. In this configuration, the hypervisor is
      the one performing the bus initialization for the purposes of bringing
      the hexagon CPU core out of reset.
      
      However, it is possible to change the configuration, in which case this
      driver will initialize the bus.
      
      In combination with drivers for resources on the SSC bus, this driver can
      aid in debugging, and for example with a TLMM driver can be used to
      directly access SSC-dedicated GPIO pins, removing the need to commit
      to a particular usecase during hw design.
      
      Finally, until open firmware for the hexagon core is available, this
      approach allows for using sensors hooked up to SSC-dedicated GPIO pins
      on mainline Linux simply by utilizing the existing in-tree drivers for
      these sensors.
      Signed-off-by: default avatarMichael Srba <Michael.Srba@seznam.cz>
      Reviewed-by: default avatarJeffrey Hugo <jeffrey.l.hugo@gmail.com>
      Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
      Link: https://lore.kernel.org/r/20220411072156.24451-5-michael.srba@seznam.cz
      97d485ed
    • Michael Srba's avatar
      dt-bindings: bus: add device tree bindings for qcom,ssc-block-bus · 0b9fe9b7
      Michael Srba authored
      Adds bindings for the AHB bus which exposes the SSC block in the global
      address space. This bus (and the SSC block itself) is present on certain
      qcom SoCs.
      
      In typical configuration, this bus (as some of the clocks and registers
      that we need to manipulate) is not accessible to the OS, and the
      resources on this bus are indirectly accessed by communicating with a
      hexagon CPU core residing in the SSC block. In this configuration, the
      hypervisor is the one performing the bus initialization for the purposes
      of bringing the haxagon CPU core out of reset.
      
      However, it is possible to change the configuration, in which case this
      binding serves to allow the OS to initialize the bus.
      Signed-off-by: default avatarMichael Srba <Michael.Srba@seznam.cz>
      Reviewed-by: default avatarRob Herring <robh@kernel.org>
      Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
      Link: https://lore.kernel.org/r/20220411072156.24451-4-michael.srba@seznam.cz
      0b9fe9b7
  2. 13 Apr, 2022 6 commits
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  6. 02 Apr, 2022 11 commits