- 02 Jul, 2024 9 commits
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Tim Huang authored
Add tmz support for GC 11.5.2. Signed-off-by:
Tim Huang <Tim.Huang@amd.com> Reviewed-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Tim Huang authored
This patch is to add GFXHUB 11.5.2 support. Signed-off-by:
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Tim Huang authored
Initialize GC 11.5.2 and set gfx hw configuration. Signed-off-by:
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Sunil Khatri authored
During ip dump in gfx10 the index variable is reused but is not reinitialized to 0 and this causes the index calculation to be wrong and access out of bound access. Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Sunil Khatri <sunil.khatri@amd.com> Signed-off-by:
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Jiapeng Chong authored
Avoid pointer type value compared with 0 to make code clear. ./drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c:14:12-13: WARNING comparing pointer to 0. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=9458Signed-off-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by:
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Jiapeng Chong authored
Avoid pointer type value compared with 0 to make code clear. ./drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.c:24:12-13: WARNING comparing pointer to 0. Reported-by:
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Jiapeng Chong authored
Avoid pointer type value compared with 0 to make code clear. ./drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_factory.c:19:12-13: WARNING comparing pointer to 0. Reported-by:
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Jiapeng Chong authored
Avoid pointer type value compared with 0 to make code clear. ./drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.c:31:12-13: WARNING comparing pointer to 0. Reported-by:
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Jiapeng Chong authored
The return value from the call to dml21_find_dc_pipes_for_plane() is int. However, the return value is being assigned to an unsigned int variable 'num_pipes', the condition if(num_pipes <= 0) is not rigorous enough, so making 'num_pipes' an int. ./drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c:318:6-15: WARNING: Unsigned expression compared with zero: num_pipes <= 0. ./drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c:360:6-15: WARNING: Unsigned expression compared with zero: num_pipes <= 0. Reported-by:
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- 01 Jul, 2024 31 commits
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Marek Olšák authored
There were multiple bugs, like checking SWIZZLE_MODE before checking GFX12_SWIZZLE_MODE, which has undefined behavior. The function had no effect before (it always returned -EINVAL). Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Acked-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by:
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Pierre-Eric Pelloux-Prayer authored
The call to radeon_vm_clear_freed might clear bo_va->bo, so we have to check it before dereferencing it. Signed-off-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Acked-by:
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Lijo Lazar authored
Convert some pr_* to some dev_* APIs to identify the device. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
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Hawking Zhang authored
To align with firmware, hbm id field 0x1 refers to hbm stack 0, 0x2 refers to hbm statck 1. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Marek Olšák authored
amdgpu_framebuffer doesn't have tiling_flags, so we need this. amdgpu_display_get_fb_info never gets NULL parameters, so checking for NULL was useless. Signed-off-by:
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Marek Olšák authored
Signed-off-by:
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Marek Olšák authored
It used gfx9 flags, which has undefined behavior on gfx12. Signed-off-by:
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Marek Olšák authored
All this code has undefined behavior on GFX12 and shouldn't be executed. Signed-off-by:
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Marek Olšák authored
It verified GFX9-11 swizzle modes on GFX12, which has undefined behavior. Signed-off-by:
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Hawking Zhang authored
Driver should write to fault_cntl registers to do one-shot address/status clear. Signed-off-by:
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Marek Olšák authored
It only uses fields for GFX9-11 related to the separate DCC buffer, which doesn't exist in GFX12. Signed-off-by:
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Marek Olšák authored
Checking SWIZZLE_MODE has undefined behavior on gfx12. Signed-off-by:
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Marek Olšák authored
They were added accidentally. Signed-off-by:
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Marek Olšák authored
GDS doesn't exist in gfx12. The incomplete packet allows userspace to hang the hw from the kernel. Signed-off-by:
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Marek Olšák authored
If any INV flags are needed, they should be executed via ACQUIRE_MEM before INDIRECT_BUFFER. GLM flags are also removed because the hw ignores them. Signed-off-by:
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Marek Olšák authored
If any INV flags are needed, they should be executed via ACQUIRE_MEM before INDIRECT_BUFFER. Signed-off-by:
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Marek Olšák authored
Fix incorrect check. Signed-off-by:
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Aric Cyr authored
* FW Release 0.0.224.0 * Fix bw issue for dcn351 * Fix FAMS2 logic issue for dcn401 * Fix Coverity issues * Fix cursor issues * Refactor dio sources Acked-by:
Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by:
Jerry Zuo <jerry.zuo@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Roman Li authored
[Why] Potential out of bounds access in dml2_calculate_rq_and_dlg_params() because the value of out_lowest_state_idx used as an index for FCLKChangeSupport array can be greater than 1. [How] Currently dml2 core specifies identical values for all FCLKChangeSupport elements. Always use index 0 in the condition to avoid out of bounds access. Acked-by:
Roman Li <Roman.Li@amd.com> Tested-by:
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Fangzhi Zuo authored
Fix 4k240 underflow on dcn351 Acked-by:
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Tom Chung authored
[Why] Some of the panels does not have the refresh rate range info in base EDID and only have the refresh rate range info in DisplayID block. It will cause the max/min freesync refresh rate set to 0. [How] Try to parse the refresh rate range info from DisplayID if the max/min refresh rate is 0. Reviewed-by:
Sun peng Li <sunpeng.li@amd.com> Signed-off-by:
Tom Chung <chiahsuan.chung@amd.com> Tested-by:
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Xi (Alex) Liu authored
[Why] In OTG disable workarund, CRTC is disabled immediately to improve performance, but this may cause timing issue in DP HPO encoder FIFO and result in blank CRCs. [How] Replace the immediate CRTC disable call with normal disable call Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
Xi (Alex) Liu <xi.liu@amd.com> Tested-by:
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Bhuvanachandra Pinninti authored
[why] Refactor the code of dio to unit test. [how] Moved files to respective folders and changed cMakeLists and makefiles. Acked-by:
Bhuvanachandra Pinninti <bpinnint@amd.com> Tested-by:
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Alvin Lee authored
[Description] We need to ensure to take into account cursor prefetch BW in mode support or we may pass ModeQuery but fail an actual flip which will cause a hang. Flip may fail because the cursor_pre_bw is populated during mode programming (and mode programming is never called prior to ModeQuery). Reviewed-by:
Chaitanya Dhere <chaitanya.dhere@amd.com> Reviewed-by:
Nevenko Stupar <nevenko.stupar@amd.com> Signed-off-by:
Alvin Lee <alvin.lee2@amd.com> Tested-by:
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Wenjing Liu authored
[why] The function enumerates all pipes without checking pipe type. It is only supposed to call program pixel clock for OTG master pipe only. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Tested-by:
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Fangzhi Zuo authored
Reset fams stream count upon stream removal, otherwise fams2 state machine in dmub will get corrupted. Reviewed-by:
Dillon Varone <dillon.varone@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] DM can hook this up to disable SLDO optimizations in firmware during DMCUB initialization for debug purposes. [How] Add the option and pass it through dmub_srv. Reviewed-by:
Hansen Dsouza <hansen.dsouza@amd.com> Signed-off-by:
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Paul Hsieh authored
[Why] Driver doesn't validate multi-display with scaling when OS calls DDI. This behavior causes the validated result to be a mismatch between some automated test cases. To address this issue, some workaround was added that caused issues in 8k. [How] Since the origin issue had been root caused, revert the previous workaround and unblock 8k with a single dimm. Reviewed-by:
Paul Hsieh <paul.hsieh@amd.com> Tested-by:
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Ryan Seto authored
[Why] Audio for 8K 240Hz monitor was not available when it should be [How] Added calculation based on stream state Co-developed-by:
Ryan Seto <ryanseto@amd.com> Reviewed-by:
George Shen <george.shen@amd.com> Signed-off-by:
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Tom Chung authored
[Why] We only enable the VRR while monitor usable refresh rate range is greater than 10 Hz. But we did not check the range in DRM_EDID_FEATURE_CONTINUOUS_FREQ case. [How] Add a refresh rate range check before set the freesync_capable flag in DRM_EDID_FEATURE_CONTINUOUS_FREQ case. Reviewed-by:
Mario Limonciello <mario.limonciello@amd.com> Reviewed-by:
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Dillon Varone authored
[WHY&HOW] Cleanup unnecessary code pathes as compile guards were added and removed overtime. Reviewed-by:
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