1. 30 Oct, 2017 15 commits
    • Adrian Hunter's avatar
      mmc: mmc: Enable Command Queuing · 98d4f780
      Adrian Hunter authored
      Enable the Command Queue if the host controller supports a command queue
      engine. It is not compatible with Packed Commands, so make a note of that in the
      comment.
      Signed-off-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
      Reviewed-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
      98d4f780
    • Adrian Hunter's avatar
      mmc: core: Add support for handling CQE requests · 72a5af55
      Adrian Hunter authored
      Add core support for handling CQE requests, including starting, completing
      and recovering.
      Signed-off-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
      Reviewed-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
      72a5af55
    • Adrian Hunter's avatar
      mmc: core: Introduce host claiming by context · 6c0cedd1
      Adrian Hunter authored
      Currently the host can be claimed by a task.  Change this so that the host
      can be claimed by a context that may or may not be a task.  This provides
      for the host to be claimed by a block driver queue to support blk-mq, while
      maintaining compatibility with the existing use of mmc_claim_host().
      Signed-off-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
      Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
      6c0cedd1
    • Adrian Hunter's avatar
      mmc: core: Remove unnecessary host claim · 9ca28c5c
      Adrian Hunter authored
      Callers already have the host claimed, so remove the unnecessary
      calls to mmc_claim_host() and mmc_release_host().
      Signed-off-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
      Reviewed-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
      9ca28c5c
    • Linus Walleij's avatar
      mmc: block: Fix bug when removing RPMB chardev · 1c87f735
      Linus Walleij authored
      I forgot to account for the fact that the device core holds a
      reference to a device added with device_initialize() that need
      to be released with a corresponding put_device() to reach a 0
      refcount at the end of the lifecycle.
      
      This led to a NULL pointer reference when freeing the device
      when e.g. unbidning the host device in sysfs.
      
      Fix this and use the device .release() callback to free the
      IDA and free:ing the memory used by the RPMB device.
      
      Before this patch:
      
      /sys/bus/amba/drivers/mmci-pl18x$ echo 80114000.sdi4_per2 > unbind
      [   29.797332] mmc3: card 0001 removed
      [   29.810791] Unable to handle kernel NULL pointer dereference at
                     virtual address 00000050
      [   29.818878] pgd = de70c000
      [   29.821624] [00000050] *pgd=1e70a831, *pte=00000000, *ppte=00000000
      [   29.827911] Internal error: Oops: 17 [#1] PREEMPT SMP ARM
      [   29.833282] Modules linked in:
      [   29.836334] CPU: 1 PID: 154 Comm: sh Not tainted
                     4.14.0-rc3-00039-g83318e309566-dirty #736
      [   29.844604] Hardware name: ST-Ericsson Ux5x0 platform (Device Tree Support)
      [   29.851562] task: de572700 task.stack: de742000
      [   29.856079] PC is at kernfs_find_ns+0x8/0x100
      [   29.860443] LR is at kernfs_find_and_get_ns+0x30/0x48
      
      After this patch:
      
      /sys/bus/amba/drivers/mmci-pl18x$ echo 80005000.sdi4_per2 > unbind
      [   20.623382] mmc3: card 0001 removed
      
      Fixes: 97548575 ("mmc: block: Convert RPMB to a character device")
      Reported-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
      Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      Acked-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
      Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
      1c87f735
    • Linus Walleij's avatar
      mmc: block: Delete mmc_access_rpmb() · 14f4ca7e
      Linus Walleij authored
      This function is used by the block layer queue to bail out of
      requests if the current request is towards an RPMB
      "block device".
      
      This was done to avoid boot time scanning of this "block
      device" which was never really a block device, thus duct-taping
      over the fact that it was badly engineered.
      
      This problem is now gone as we removed the offending RPMB block
      device in another patch and replaced it with a character
      device.
      
      Cc: Tomas Winkler <tomas.winkler@intel.com>
      Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
      14f4ca7e
    • Linus Walleij's avatar
      mmc: block: Convert RPMB to a character device · 97548575
      Linus Walleij authored
      The RPMB partition on the eMMC devices is a special area used
      for storing cryptographically safe information signed by a
      special secret key. To write and read records from this special
      area, authentication is needed.
      
      The RPMB area is *only* and *exclusively* accessed using
      ioctl():s from userspace. It is not really a block device,
      as blocks cannot be read or written from the device, also
      the signed chunks that can be stored on the RPMB are actually
      256 bytes, not 512 making a block device a real bad fit.
      
      Currently the RPMB partition spawns a separate block device
      named /dev/mmcblkNrpmb for each device with an RPMB partition,
      including the creation of a block queue with its own kernel
      thread and all overhead associated with this. On the Ux500
      HREFv60 platform, for example, the two eMMCs means that two
      block queues with separate threads are created for no use
      whatsoever.
      
      I have concluded that this block device design for RPMB is
      actually pretty wrong. The RPMB area should have been designed
      to be accessed from /dev/mmcblkN directly, using ioctl()s on
      the main block device. It is however way too late to change
      that, since userspace expects to open an RPMB device in
      /dev/mmcblkNrpmb and we cannot break userspace.
      
      This patch tries to amend the situation using the following
      strategy:
      
      - Stop creating a block device for the RPMB partition/area
      
      - Instead create a custom, dynamic character device with
        the same name.
      
      - Make this new character device support exactly the same
        set of ioctl()s as the old block device.
      
      - Wrap the requests back to the same ioctl() handlers, but
        issue them on the block queue of the main partition/area,
        i.e. /dev/mmcblkN
      
      We need to create a special "rpmb" bus type in order to get
      udev and/or busybox hot/coldplug to instantiate the device
      node properly.
      
      Before the patch, this appears in 'ps aux':
      
      101 root       0:00 [mmcqd/2rpmb]
      123 root       0:00 [mmcqd/3rpmb]
      
      After applying the patch these surplus block queue threads
      are gone, but RPMB is as usable as ever using the userspace
      MMC tools, such as 'mmc rpmb read-counter'.
      
      We get instead those dynamice devices in /dev:
      
      brw-rw----    1 root     root      179,   0 Jan  1  2000 mmcblk0
      brw-rw----    1 root     root      179,   1 Jan  1  2000 mmcblk0p1
      brw-rw----    1 root     root      179,   2 Jan  1  2000 mmcblk0p2
      brw-rw----    1 root     root      179,   5 Jan  1  2000 mmcblk0p5
      brw-rw----    1 root     root      179,   8 Jan  1  2000 mmcblk2
      brw-rw----    1 root     root      179,  16 Jan  1  2000 mmcblk2boot0
      brw-rw----    1 root     root      179,  24 Jan  1  2000 mmcblk2boot1
      crw-rw----    1 root     root      248,   0 Jan  1  2000 mmcblk2rpmb
      brw-rw----    1 root     root      179,  32 Jan  1  2000 mmcblk3
      brw-rw----    1 root     root      179,  40 Jan  1  2000 mmcblk3boot0
      brw-rw----    1 root     root      179,  48 Jan  1  2000 mmcblk3boot1
      brw-rw----    1 root     root      179,  33 Jan  1  2000 mmcblk3p1
      crw-rw----    1 root     root      248,   1 Jan  1  2000 mmcblk3rpmb
      
      Notice the (248,0) and (248,1) character devices for RPMB.
      
      Cc: Tomas Winkler <tomas.winkler@intel.com>
      Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
      97548575
    • yangbo lu's avatar
      mmc: sdhci-of-esdhc: disable SD clock for clock value 0 · dd3f6983
      yangbo lu authored
      SD clock should be disabled for clock value 0. It's not
      right to just return. This may cause failure of signal
      voltage switching.
      Signed-off-by: default avatarYangbo Lu <yangbo.lu@nxp.com>
      Acked-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
      Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
      dd3f6983
    • Adrian Hunter's avatar
      mmc: sdhci-pci: Add support for Intel CDF · cdaba732
      Adrian Hunter authored
      Add PCI Id for Intel CDF.
      Signed-off-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
      Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
      cdaba732
    • Wolfram Sang's avatar
      mmc: sdhci-pci: remove outdated declaration · 79ea73b0
      Wolfram Sang authored
      The function was removed half a year ago, so this declaration can go,
      too.
      
      Fixes: 51ced59c ("mmc: sdhci-pci: Use ACPI DSM to get driver strength for some Intel devices")
      Signed-off-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
      Acked-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
      Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
      79ea73b0
    • Bjorn Andersson's avatar
      mmc: sdhci-msm: Enable delay circuit calibration clocks · 4946b3af
      Bjorn Andersson authored
      The delay circuit used to support HS400 is calibrated based on two
      additional clocks. When these clocks are not available and
      FF_CLK_SW_RST_DIS is not set in CORE_HC_MODE, reset might fail. But on
      some platforms this doesn't work properly and below dump can be seen in
      the kernel log.
      
        mmc0: Reset 0x1 never completed.
        mmc0: sdhci: ============ SDHCI REGISTER DUMP ===========
        mmc0: sdhci: Sys addr:  0x00000000 | Version:  0x00001102
        mmc0: sdhci: Blk size:  0x00004000 | Blk cnt:  0x00000000
        mmc0: sdhci: Argument:  0x00000000 | Trn mode: 0x00000000
        mmc0: sdhci: Present:   0x01f80000 | Host ctl: 0x00000000
        mmc0: sdhci: Power:     0x00000000 | Blk gap:  0x00000000
        mmc0: sdhci: Wake-up:   0x00000000 | Clock:    0x00000002
        mmc0: sdhci: Timeout:   0x00000000 | Int stat: 0x00000000
        mmc0: sdhci: Int enab:  0x00000000 | Sig enab: 0x00000000
        mmc0: sdhci: AC12 err:  0x00000000 | Slot int: 0x00000000
        mmc0: sdhci: Caps:      0x742dc8b2 | Caps_1:   0x00008007
        mmc0: sdhci: Cmd:       0x00000000 | Max curr: 0x00000000
        mmc0: sdhci: Resp[0]:   0x00000000 | Resp[1]:  0x00000000
        mmc0: sdhci: Resp[2]:   0x00000000 | Resp[3]:  0x00000000
        mmc0: sdhci: Host ctl2: 0x00000000
        mmc0: sdhci: ============================================
      
      Add support for the additional calibration clocks to allow these
      platforms to be configured appropriately.
      
      Cc: Venkat Gopalakrishnan <venkatg@codeaurora.org>
      Cc: Ritesh Harjani <riteshh@codeaurora.org>
      Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
      Acked-by: default avatarRob Herring <robh@kernel.org>
      Tested-by: default avatarJeremy McNicoll <jeremymc@redhat.com>
      Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
      4946b3af
    • Bjorn Andersson's avatar
      mmc: sdhci-msm: Utilize bulk clock API · e4bf91f6
      Bjorn Andersson authored
      By stuffing the runtime controlled clocks into a clk_bulk_data array we
      can utilize the newly introduced bulk clock operations and clean up the
      error paths. This allow us to handle additional clocks in subsequent
      patch, without the added complexity.
      
      Cc: Ritesh Harjani <riteshh@codeaurora.org>
      Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
      Tested-by: default avatarJeremy McNicoll <jeremymc@redhat.com>
      Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
      e4bf91f6
    • Krishna Reddy's avatar
      mmc: tegra: Mark 64 bit dma broken on Tegra186 · 68481a7e
      Krishna Reddy authored
      SDHCI controllers on Tegra186 support 40 bit addressing.
      IOVA addresses are 48-bit wide on Tegra186.
      SDHCI host common code sets dma mask as either 32-bit or 64-bit.
      To avoid access issues when SMMU is enabled, disable 64-bit dma.
      Signed-off-by: default avatarKrishna Reddy <vdumpa@nvidia.com>
      Tested-by: default avatarThierry Reding <treding@nvidia.com>
      Acked-by: default avatarThierry Reding <treding@nvidia.com>
      Acked-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
      Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
      68481a7e
    • Ulf Hansson's avatar
      Merge branch 'fixes' into next · faf73fa1
      Ulf Hansson authored
      faf73fa1
    • Ulf Hansson's avatar
      Merge branch 'omap_hsmmc' into next · 35ed78a0
      Ulf Hansson authored
      35ed78a0
  2. 29 Oct, 2017 25 commits