Commits · 99349a8aeda7a044fc5850924bc3b57c306a1553 · Kirill Smelkov / linux

01 Dec, 2020 17 commits

drm/amd/display: Init clock value by current vbios CLKs · 99349a8a

Brandon Syu authored Nov 12, 2020

[Why]
While booting into OS, driver updates DPP/DISP CLKs.
But init clock value is zero which is invalid.

[How]
Get current clocks value to update init clocks.
To avoid underflow.
Signed-off-by: Brandon Syu <Brandon.Syu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

99349a8a

drm/amd/display: Check link_active instead of lane_settings != unknown · 07920450

Joshua Aberback authored Nov 17, 2020

[Why]
enable_link_dp_mst checks that cur_link_settings != unknown to determine
that the link is already enabled, to skip redundant enablement calls for
multiple streams on the same link. During dc_reinitialize_hardware,
cur_link_settings on previously-active links is not cleared, which blocks
MST links from being re-enabled after a reinitialization.

[How]
 - check for link_status->link_active instead, as it's the real intent
 - clear cur_link_settings when we clear link_active
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

07920450

drm/amd/display: Update dram_clock_change_latency for DCN2.1 · 901c1ec0

Sung Lee authored Nov 13, 2020

[WHY]
dram clock change latencies get updated using ddr4 latency table, but
does that update does not happen before validation. This value
should not be the default and should be number received from
df for better mode support.
This may cause a PState hang on high refresh panels with short vblanks
such as on 1080p 360hz or 300hz panels.

[HOW]
Update latency from 23.84 to 11.72.
Signed-off-by: Sung Lee <sung.lee@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

901c1ec0

drm/amd/display: Add HDR3DLUT and SHAPER memory shutdown support · 00b0ac67

Jacky Liao authored Nov 13, 2020

[Why]
The HDR3DLUT and SHAPER memory blocks should be powered down when
they're not in use. This will reduce power consumption.

[How]
1. Write to HDR3DLUT_MEM_PWR_FORCE to put memory to shutdown
   when HDR3DLUT is not used.
2. Write to SHAPER_MEM_PWR_FORCE to put memory to shutdown
   when SHAPER is not used.
Signed-off-by: Jacky Liao <ziyu.liao@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

00b0ac67

drm/amd/display: Revert update clk_mgr for vg · bc1e0894

Eric Bernstein authored Nov 12, 2020

This reverts commit 2208f39c.
It caused a regression in internal FPGA tests.
Signed-off-by: Eric Bernstein <Eric.Bernstein@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

bc1e0894

drm/amdgpu: set LDS_CONFIG=0x20 on VanGogh to fix MGCG hang · 0c056b14

Marek Olšák authored Nov 25, 2020

Same as Sienna Cichlid and Navy Flounder.
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

0c056b14

drm/amd/display: turn DPMS off on connector unplug · 3c4d55c9

Aurabindo Pillai authored Nov 26, 2020

[Why&How]

Set dpms off on the connector that was unplugged, for the side effect of
releasing some references held through deallocation of MST payload. This is
the expected behaviour for non MST devices as well.
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Eryk Brol <eryk.brol@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

3c4d55c9

drm/amd/display: Clear dc remote sinks on MST disconnect · 3f16ae82

Aurabindo Pillai authored Nov 26, 2020

[Why&How]
Recent changes to upstream mst code remove the callback which
cleared the internal state for mst. Move the missing functionality
that was previously called through the destroy call back for mst connector
destroy
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Eryk Brol <eryk.brol@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

3f16ae82

drm/amdgpu/pm/smu11: Fix fan set speed bug · 22dd8982

Arunpravin authored Nov 27, 2020

Fix fan set speed calculation.
Suggested-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Arunpravin <Arunpravin.PaneerSelvam@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

22dd8982

drm/amdgpu: Set doorbell range for gfx ring · 79c77ac6

Jinzhou Su authored Nov 27, 2020

If there are 2 gfx rings, the doorbell lower range of second ring
will override the first ring.
Signed-off-by: Jinzhou.Su <Jinzhou.Su@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

79c77ac6

drm/amdgpu: update GC golden setting for dimgrey_cavefish · 3591ecd6

Tao Zhou authored Nov 27, 2020

Update GC golden setting for dimgrey_cavefish.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

3591ecd6

drm/amdgpu: skip power profile switch in sriov · 7cf7a392

Jingwen Chen authored Nov 24, 2020

power profile switch in vcn need to send SetWorkLoad msg to
smu, which is not supported in sriov.
Signed-off-by: Jingwen Chen <Jingwen.Chen2@amd.com>
Reviewed-by: Jiange Zhao <Jiange.Zhao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

7cf7a392

drm/amd/pm: update driver if version for navy_flounder · d503d8b8

Jiansong Chen authored Nov 26, 2020

It's in accordance with pmfw 65.18.0 for navy_flounder.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

d503d8b8

drm/amdgpu/vcn3.0: fix compilation warning · 91a7f887

James Zhu authored Nov 25, 2020

Fixed warning: no previous prototype.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reported-by: kernel test robot <lkp@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

91a7f887

drm/amdgpu: increase reserved VRAM size to 8MB · 8c8244ca

Likun Gao authored Nov 25, 2020

4MB reserved VRAM size which used for page tables was not enough for
some condition, increase it to 8MB to reduce page table contention.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

8c8244ca

drm/amdgpu: only skip smc sdma sos ta and asd fw in SRIOV for navi12 · 055e94a8

Stanley.Yang authored Nov 20, 2020

The KFDTopologyTest.BasicTest will failed if skip smc, sdma, sos, ta
and asd fw in SRIOV for vega10, so adjust above fw and skip load them
in SRIOV only for navi12.

v2: remove unnecessary asic type check.
Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

055e94a8

drm/amdgpu: set default value of noretry to 1 for specified asic · 9ccde05c

Stanley.Yang authored Nov 23, 2020

noretry = 0 casue KFDGraphicsInterop test failed
on SRIOV platform for vega10, so set noretry to 1
for vega10.
Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

9ccde05c

24 Nov, 2020 23 commits

drm/amd/powerplay: fix spelling mistake "smu_state_memroy_block" -> "smu_state_memory_block" · beaff108

Colin Ian King authored Nov 23, 2020

The struct name smu_state_memroy_block contains a spelling mistake, rename
it to smu_state_memory_block

Fixes: 8554e67d ("drm/amd/powerplay: implement power_dpm_state sys interface for SMU11")
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>