- 23 Jul, 2020 15 commits
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Laurentiu Tudor authored
Replace the spinlock that serializes the MC commands with a raw spinlock. This is needed for the RT kernel because there are MC commands sent in interrupt context. Signed-off-by:
Laurentiu Tudor <laurentiu.tudor@nxp.com> Signed-off-by:
Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Ioana Ciornei authored
The MC bus has different types of devices that can be discovered on the bus. Add the missing device types. Signed-off-by:
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Vaibhav Gupta authored
Drivers should not use legacy power management as they have to manage power states and related operations, for the device, themselves. This driver was handling them with the help of PCI helper functions like pci_save/restore_state(), pci_enable/disable_device(), etc. With generic PM, all essentials will be handled by the PCI core. Driver needs to do only device-specific operations. The driver was also using pci_enable_wake(...,..., 0) to disable wake. Use device_wakeup_disable() instead. Compile-tested only. Signed-off-by:
Vaibhav Gupta <vaibhavgupta40@gmail.com> Link: https://lore.kernel.org/r/20200720101722.145211-1-vaibhavgupta40@gmail.comSigned-off-by:
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Christophe JAILLET authored
Avoid a memset after a call to 'dma_alloc_coherent()'. This is useless since commit 518a2f19 ("dma-mapping: zero memory returned from dma_alloc_*") Signed-off-by:
Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/20200718070246.338016-1-christophe.jaillet@wanadoo.frSigned-off-by:
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Christophe JAILLET authored
The wrappers in include/linux/pci-dma-compat.h should go away. The patch has been generated with the coccinelle script below and has been hand modified to replace GFP_ with a correct flag. It has been compile tested. When memory is allocated in 'ilo_ccb_setup()' GFP_ATOMIC must be used because a spin_lock is hold in 'ilo_open()' before calling 'ilo_ccb_setup()' @@ @@ - PCI_DMA_BIDIRECTIONAL + DMA_BIDIRECTIONAL @@ @@ - PCI_DMA_TODEVICE + DMA_TO_DEVICE @@ @@ - PCI_DMA_FROMDEVICE + DMA_FROM_DEVICE @@ @@ - PCI_DMA_NONE + DMA_NONE @@ expression e1, e2, e3; @@ - pci_alloc_consistent(e1, e2, e3) + dma_alloc_coherent(&e1->dev, e2, e3, GFP_) @@ expression e1, e2, e3; @@ - pci_zalloc_consistent(e1, e2, e3) + dma_alloc_coherent(&e1->dev, e2, e3, GFP_) @@ expression e1, e2, e3, e4; @@ - pci_free_consistent(e1, e2, e3, e4) + dma_free_coherent(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_map_single(e1, e2, e3, e4) + dma_map_single(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_unmap_single(e1, e2, e3, e4) + dma_unmap_single(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4, e5; @@ - pci_map_page(e1, e2, e3, e4, e5) + dma_map_page(&e1->dev, e2, e3, e4, e5) @@ expression e1, e2, e3, e4; @@ - pci_unmap_page(e1, e2, e3, e4) + dma_unmap_page(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_map_sg(e1, e2, e3, e4) + dma_map_sg(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_unmap_sg(e1, e2, e3, e4) + dma_unmap_sg(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_dma_sync_single_for_cpu(e1, e2, e3, e4) + dma_sync_single_for_cpu(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_dma_sync_single_for_device(e1, e2, e3, e4) + dma_sync_single_for_device(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_dma_sync_sg_for_cpu(e1, e2, e3, e4) + dma_sync_sg_for_cpu(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_dma_sync_sg_for_device(e1, e2, e3, e4) + dma_sync_sg_for_device(&e1->dev, e2, e3, e4) @@ expression e1, e2; @@ - pci_dma_mapping_error(e1, e2) + dma_mapping_error(&e1->dev, e2) @@ expression e1, e2; @@ - pci_set_dma_mask(e1, e2) + dma_set_mask(&e1->dev, e2) @@ expression e1, e2; @@ - pci_set_consistent_dma_mask(e1, e2) + dma_set_coherent_mask(&e1->dev, e2) Signed-off-by:
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Greg Kroah-Hartman authored
Merge tag 'phy-for-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into char-misc-next Vinod writes: phy for 5.9 - New PHY Drivers: - Samsung UFS - Qcom USB DWC for ipq806x - Xilinx ZynqMP Gigabit Transceiver - Qcom USB QMP for IPQ8074 - BCM63xx USBH - Removed: - Qcom ufs qmp phy driver - Updates: - Support for Qcom SM8250 QMP V4 USB3 UNIPHY - qcom-snps runtime pm support - Cleanup of W=1 warns in the subsystem * tag 'phy-for-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (46 commits) phy: qualcomm: fix setting of tx_deamp_3_5db when device property read fails phy: bcm63xx-usbh: Add BCM63xx USBH driver dt-bindings: phy: add bcm63xx-usbh bindings phy: armada-38x: fix NETA lockup when repeatedly switching speeds dt: update Marvell Armada 38x COMPHY binding phy: samsung-ufs: Fix IS_ERR argument dt-bindings: phy: renesas,usb3-phy: Add r8a774e1 support dt-bindings: phy: renesas,usb2-phy: Add r8a774e1 support phy: renesas: rcar-gen3-usb2: exit if request_irq() failed phy: renesas: rcar-gen3-usb2: move irq registration to init devicetree: bindings: phy: Document ipq806x dwc3 qcom phy phy: qualcomm: add qcom ipq806x dwc usb phy driver phy: samsung-ufs: add UFS PHY driver for samsung SoC dt-bindings: phy: Document Samsung UFS PHY bindings phy: sun4i-usb: explicitly include gpio/consumer.h phy: stm32: use NULL instead of zero phy: exynos5-usbdrd: use correct format for structure description phy: rockchip-typec: use correct format for structure description phy: xgene: remove unsigned integer comparison with less than zero phy: mapphone-mdm6600: Add missing description for some structure fields ...
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Alexander A. Klimov authored
Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by:Alexander A. Klimov <grandmaster@al2klimov.de> Link: https://lore.kernel.org/r/20200713104453.33414-1-grandmaster@al2klimov.deSigned-off-by:
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Alexander A. Klimov authored
Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by: -
Randy Dunlap authored
Drop the repeated word "the" in a comment. Cc: Arve Hjønnevåg <arve@android.com> Cc: Todd Kjos <tkjos@android.com> Cc: Martijn Coenen <maco@android.com> Cc: Joel Fernandes <joel@joelfernandes.org> Cc: Hridya Valsaraju <hridya@google.com> Cc: Suren Baghdasaryan <surenb@google.com> Cc: devel@driverdev.osuosl.org Acked-by:
Christian Brauner <christian.brauner@ubuntu.com> Signed-off-by:
Randy Dunlap <rdunlap@infradead.org> Link: https://lore.kernel.org/r/20200719002738.20210-1-rdunlap@infradead.orgSigned-off-by:
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Randy Dunlap authored
Drop the repeated word "the" in a comment. Signed-off-by:
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Gustavo A. R. Silva authored
One-element arrays are being deprecated[1]. Replace the one-element arrays with a simple value type u8 reserved, once this is just a placeholder for alignment. Also, while there, use the preferred form for passing a size of a struct. The alternative form where struct name is spelled out hurts readability and introduces an opportunity for a bug when the variable type is changed but the corresponding sizeof that is passed as argument is not. [1] https://github.com/KSPP/linux/issues/79Signed-off-by:
Gustavo A. R. Silva <gustavoars@kernel.org> Link: https://lore.kernel.org/r/20200714214516.GA1040@embeddedorSigned-off-by:
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Alexander A. Klimov authored
Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by:Tomas Winkler <tomas.winkler@intel.com> Link: https://lore.kernel.org/r/20200717185925.84102-1-grandmaster@al2klimov.deSigned-off-by:
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Gustavo A. R. Silva authored
There is a regular need in the kernel to provide a way to declare having a dynamically sized set of trailing elements in a structure. Kernel code should always use “flexible array members”[1] for these cases. The older style of one-element or zero-length arrays should no longer be used[2]. Also, make use of the array_size() helper instead of the open-coded version in memcpy(). These sorts of multiplication factors need to be wrapped in array_size(). And while there, use the preferred form for passing a size of a struct. The alternative form where struct name is spelled out hurts readability and introduces an opportunity for a bug when the pointer variable type is changed but the corresponding sizeof that is passed as argument is not. [1] https://en.wikipedia.org/wiki/Flexible_array_member [2] https://github.com/KSPP/linux/issues/79Signed-off-by:
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Greg Kroah-Hartman authored
Merge tag 'fpga-for-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga into char-misc-next Moritz writes: FPGA Manager changes for 5.9-rc1 Here is the (slightly larger than usual) patch set for the 5.9-rc1 merge window. DFL: - Xu's changes add support for AFU interrupt handling and puts them to use for error handling. - Xu's other change also adds another device-id for the Intel FPGA PAC N3000. - John's change converts from using get_user_pages() to pin_user_pages(). - Gustavo's patch cleans up some of the allocation by using struct_size(). Xilinx: - Luca's changes clean up the xilinx-spi and xilinx-slave-serial drivers and updates the comments and dt-bindings to reflect the fact it also supports 7 series devices. Core: - Tom cleaned up the fpga-bridge / fpga-mgr core by removing some dead-stores. All patches have been reviewed on the mailing list, and have been in the last few linux-next releases (as part of my for-next branch) without issues. Signed-off-by:
Moritz Fischer <mdf@kernel.org> * tag 'fpga-for-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/mdf/linux-fpga: fpga: dfl: pci: add device id for Intel FPGA PAC N3000 Documentation: fpga: dfl: add descriptions for interrupt related interfaces. fpga: dfl: afu: add AFU interrupt support fpga: dfl: fme: add interrupt support for global error reporting fpga: dfl: afu: add interrupt support for port error reporting fpga: dfl: introduce interrupt trigger setting API fpga: dfl: pci: add irq info for feature devices enumeration fpga: dfl: parse interrupt info for feature devices on enumeration fpga manager: xilinx-spi: check INIT_B pin during write_init dt-bindings: fpga: xilinx-slave-serial: add optional INIT_B GPIO fpga: Fix dead store in fpga-bridge.c fpga: Fix dead store fpga-mgr.c fpga: dfl: Use struct_size() in kzalloc() fpga manager: xilinx-spi: remove unneeded, mistyped variables fpga manager: xilinx-spi: valid for the 7 Series too dt-bindings: fpga: xilinx-slave-serial: valid for the 7 Series too fpga: dfl: afu: convert get_user_pages() --> pin_user_pages()
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Greg Kroah-Hartman authored
Merge tag 'soundwire-5.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire into char-misc-next Vinod writes: soundwire updates for 5.9-rc1 This contains few core changes and bunch of Intel driver updates: - Adds definitions for 1.2 spec - Sanyog left as a MAINTAINER and Bard took his place while Sanyog is a reviewer now. - Intel: Lots of updates to stream/dai handling, wake support and link synchronization. * tag 'soundwire-5.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire: (31 commits) Soundwire: intel_init: save Slave(s) _ADR info in sdw_intel_ctx soundwire: intel: add wake interrupt support soundwire: intel/cadence: merge Soundwire interrupt handlers/threads soundwire: intel_init: use EXPORT_SYMBOL_NS soundwire: intel_init: add implementation of sdw_intel_enable_irq() soundwire: intel: introduce helper for link synchronization soundwire: intel: introduce a helper to arm link synchronization soundwire: intel: revisit SHIM programming sequences. soundwire: intel: reuse code for wait loops to set/clear bits soundwire: fix the kernel-doc comment soundwire: sdw.h: fix indentation soundwire: sdw.h: fix PRBS/Static_1 swapped definitions soundwire: intel: don't free dma_data in DAI shutdown soundwire: cadence: allocate/free dma_data in set_sdw_stream soundwire: intel: remove stream allocation/free soundwire: stream: add helper to startup/shutdown streams soundwire: intel: implement get_sdw_stream() operations MAINTAINERS: change SoundWire maintainer soundwire: bus: initialize bus clock base and scale registers soundwire: extend SDW_SLAVE_ENTRY ...
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- 22 Jul, 2020 5 commits
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Bjorn Helgaas authored
When reading registers defined by the PCIe spec, use the names already defined by the PCI core. This makes maintenance of the PCI core and drivers easier. No functional change intended. Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com> Acked-by:
Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20200721212336.1159079-6-helgaas@kernel.org [ additional replacements due to changes in my tree - gregkh ] Signed-off-by:
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Bjorn Helgaas authored
Instead of hard-coding the location of the L1 PM Substates capability based on the Device ID, search for it in the extended capabilities list. This works for any device, as long as it implements the L1 PM Substates capability correctly, so it doesn't require maintenance as new devices are added. No functional change intended. Signed-off-by:
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Bjorn Helgaas authored
rtsx_pci_read_config_dword() and similar wrappers around the PCI config accessors add very little value, and they obscure the fact that often we are accessing standard PCI registers that should be coordinated with the PCI core. Remove the wrappers and use the PCI config accessors directly. No functional change intended. Signed-off-by:
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Bjorn Helgaas authored
There are no more uses of struct rtsx_pcr.pcie_cap. Remove it. Signed-off-by:
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Bjorn Helgaas authored
Instead of using the driver-specific rtsx_pci_write_config_byte() to update the PCIe Link Control Register, use pcie_capability_write_word() like the rest of the kernel does. This makes it easier to maintain ASPM across the PCI core and drivers. No functional change intended. I missed this when doing 3d1e7aa8 ("misc: rtsx: Use pcie_capability_clear_and_set_word() for PCI_EXP_LNKCTL"). Signed-off-by:
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- 21 Jul, 2020 20 commits
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Colin Ian King authored
Currently when reading of the device property for "qcom,tx-deamp_3_5db" fails the default is being assigned incorrectly to phy_dwc3->rx_eq. This looks like a copy-n-paste error and in fact should be assigning the default instead to phy_dwc3->tx_deamp_3_5db Addresses-Coverity: ("Copy-paste error") Fixes: ef19b117 ("phy: qualcomm: add qcom ipq806x dwc usb phy driver") Signed-off-by:Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20200721150613.416876-1-colin.king@canonical.comSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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Álvaro Fernández Rojas authored
Add BCM63xx USBH PHY driver for BMIPS. Signed-off-by:
Álvaro Fernández Rojas <noltari@gmail.com> Signed-off-by:
Simon Arlott <simon@octiron.net> Link: https://lore.kernel.org/r/20200720131209.1236590-3-noltari@gmail.comSigned-off-by:
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Álvaro Fernández Rojas authored
Document BCM63xx USBH PHY bindings. Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com> Reviewed-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200720131209.1236590-2-noltari@gmail.comSigned-off-by:
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Russell King authored
The mvneta hardware appears to lock up in various random ways when repeatedly switching speeds between 1G and 2.5G, which involves reprogramming the COMPHY. It is not entirely clear why this happens, but best guess is that reprogramming the COMPHY glitches mvneta clocks causing the hardware to fail. It seems that rebooting resolves the failure, but not down/up cycling the interface alone. Various other approaches have been tried, such as trying to cleanly power down the COMPHY and then take it back through the power up initialisation, but this does not seem to help. It was finally noticed that u-boot's last step when configuring a COMPHY for "SGMII" mode was to poke at a register described as "GBE_CONFIGURATION_REG", which is undocumented in any external documentation. All that we have is the fact that u-boot sets a bit corresponding to the "SGMII" lane at the end of COMPHY initialisation. Experimentation shows that if we clear this bit prior to changing the speed, and then set it afterwards, mvneta does not suffer this problem on the SolidRun Clearfog when switching speeds between 1G and 2.5G. This problem was found while script-testing phylink. This fix also requires the corresponding change to DT to be effective. See "ARM: dts: armada-38x: fix NETA lockup when repeatedly switching speeds". Fixes: 14dc100b ("phy: armada38x: add common phy support") Signed-off-by:
Russell King <rmk+kernel@armlinux.org.uk> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/E1jxtRj-0003Tz-CG@rmk-PC.armlinux.org.ukSigned-off-by:
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Russell King authored
Update the Marvell Armada 38x COMPHY binding with an additional optional register pair describing the location of an undocumented system register controlling something to do with the Gigabit Ethernet and COMPHY. There is one bit for each COMPHY lane that may be using the serdes, but exactly what this register does is completely unknown. This register only appears to exist on Armada 38x devices, and not other SoCs using the NETA ethernet block, so it seems logical that it should be part of the COMPHY. This is also how u-boot groups this register; it is dealt with as part of the COMPHY initialisation there. However, at the end of the day, due to the undocumented nature of this register, we can only guess. Signed-off-by:
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Suzuki K Poulose authored
The ETM state save/restore incorrectly reads/writes some of the 64bit registers (e.g, address comparators, vmid/cid comparators etc.) using 32bit accesses. Ensure we use the appropriate width accessors for the registers. Fixes: f188b5e7 ("coresight: etm4x: Save/restore state across CPU low power states") Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by:
Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by:
Mathieu Poirier <mathieu.poirier@linaro.org> Link: https://lore.kernel.org/r/20200716175746.3338735-18-mathieu.poirier@linaro.orgSigned-off-by:
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Mike Leach authored
Add default sink selection to the perf trace handling in the etm driver. Uses the select default sink infrastructure to select a sink for the perf session, if no other sink is specified. Signed-off-by:
Mike Leach <mike.leach@linaro.org> Reviewed-by:
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Mike Leach authored
An additional sink subtype is added to differentiate ETB/ETF buffer sinks and ETR type system memory sinks. This allows the prioritised selection of default sinks. Signed-off-by:
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Mike Leach authored
Adds a method to select a suitable sink connected to a given source. In cases where no sink is defined, the coresight_find_default_sink routine can search from a given source, through the child connections until a suitable sink is found. The suitability is defined in by the sink coresight_dev_subtype on the CoreSight device, and the distance from the source by counting connections. Higher value subtype is preferred - where these are equal, shorter distance from source is used as a tie-break. This allows for default sink to be discovered were none is specified (e.g. perf command line) Signed-off-by:
Leo Yan <leo.yan@linaro.org> Reviewed-by:
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Sai Prakash Ranjan authored
Reading TMC mode register without proper coresight power management can lead to exceptions like the one in the call trace below in tmc_read_unprepare_etb() when the trace data is read after the sink is disabled. So fix this by having a check for coresight sysfs mode before reading TMC mode management register in tmc_read_unprepare_etb() similar to tmc_read_prepare_etb(). SError Interrupt on CPU6, code 0xbe000411 -- SError pstate: 80400089 (Nzcv daIf +PAN -UAO) pc : tmc_read_unprepare_etb+0x74/0x108 lr : tmc_read_unprepare_etb+0x54/0x108 sp : ffffff80d9507c30 x29: ffffff80d9507c30 x28: ffffff80b3569a0c x27: 0000000000000000 x26: 00000000000a0001 x25: ffffff80cbae9550 x24: 0000000000000010 x23: ffffffd07296b0f0 x22: ffffffd0109ee028 x21: 0000000000000000 x20: ffffff80d19e70e0 x19: ffffff80d19e7080 x18: 0000000000000000 x17: 0000000000000000 x16: 0000000000000000 x15: 0000000000000000 x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000000 x11: 0000000000000000 x10: dfffffd000000001 x9 : 0000000000000000 x8 : 0000000000000002 x7 : ffffffd071d0fe78 x6 : 0000000000000000 x5 : 0000000000000080 x4 : 0000000000000001 x3 : ffffffd071d0fe98 x2 : 0000000000000000 x1 : 0000000000000004 x0 : 0000000000000001 Kernel panic - not syncing: Asynchronous SError Interrupt Fixes: 4525412a ("coresight: tmc: making prepare/unprepare functions generic") Reported-by:
Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Tested-by:
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Sai Prakash Ranjan authored
Implement a shutdown callback to ensure ETR hardware is properly shutdown in reboot/shutdown path. This is required for ETR which has SMMU address translation enabled like on SC7180 SoC and few others. If the hardware is still accessing memory after SMMU translation is disabled as part of SMMU shutdown callback in system reboot or shutdown path, then IOVAs(I/O virtual address) which it was using will go on the bus as the physical addresses which might result in unknown crashes (NoC/interconnect errors). So we make sure from this shutdown callback that the ETR is shutdown before SMMU translation is disabled and device_link in SMMU driver will take care of ordering of shutdown callbacks such that SMMU shutdown callback is not called before any of its consumer shutdown callbacks. Signed-off-by:
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Mike Leach authored
Comment for an elemnt in the coresight_device structure appears to have been corrupted and makes no sense. Fix this before making further changes. Signed-off-by:
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Mike Leach authored
The counter value registers change during operation, however this change is not reflected in the values seen by the user in sysfs. This fixes the issue by reading back the values on disable. Signed-off-by:
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Mike Leach authored
ETMv4 max resource selector constant incorrectly set to 16. Updated to the correct 32 value, and adjustments made to limited code using it. Signed-off-by:
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Andy Shevchenko authored
acpi_dev_get_resources() does perform the NULL pointer check against ACPI companion device which is given as function parameter. Thus, there is no need to duplicate this check in the caller. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by:
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Xu Wang authored
A multiplication for the size determination of a memory allocation indicated that an array data structure should be processed. Thus use the corresponding function "devm_kcalloc". Signed-off-by:
Xu Wang <vulab@iscas.ac.cn> Signed-off-by:
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Sai Prakash Ranjan authored
Add an optional boolean property "qcom,replicator-loses-context" to identify replicators which loses context when AMBA clocks are removed in certain configurable replicator designs. Signed-off-by:
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Sai Prakash Ranjan authored
On some QCOM SoCs, replicators in Always-On domain loses its context as soon as the clock is disabled. Currently as a part of pm_runtime workqueue, clock is disabled after the replicator is initialized by amba_pm_runtime_suspend assuming that context is not lost which is not true for replicators with such limitations. So add a new property "qcom,replicator-loses-context" to identify such replicators and reset them. Suggested-by:
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Tingwei Zhang authored
Add "qcom,skip-power-up" property to identify systems which can skip powering up of trace unit since they share the same power domain as their CPU core. This is required to identify such systems with hardware errata which stops the CPU watchdog counter when the power up bit is set (TRCPDCR.PU). Signed-off-by:
Tingwei Zhang <tingwei@codeaurora.org> Co-developed-by:
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Tingwei Zhang authored
On some Qualcomm Technologies Inc. SoCs like SC7180, there exists a hardware errata where the APSS (Application Processor SubSystem)/CPU watchdog counter is stopped when the trace unit power up ETM register is set (TRCPDCR.PU = 1). Since the ETMs share the same power domain as that of respective CPU cores, they are powered on when the CPU core is powered on. So we can skip powering up of trace unit after checking for this errata via new property called "qcom,skip-power-up". Signed-off-by:
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