- 29 Mar, 2022 3 commits
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Stephen Boyd authored
- Mark mux table as const in clk-mux - Make the all_lists array const * clk-mvebu: clk: mvebu: use time_is_before_eq_jiffies() instead of open coding it * clk-const: clk: Mark clk_core_evict_parent_cache_subtree() 'target' const clk: Mark 'all_lists' as const clk: pistachio: Declare mux table as const u32[] clk: qcom: Declare mux table as const u32[] clk: mmp: Declare mux tables as const u32[] clk: hisilicon: Remove unnecessary cast of mux table to u32 * clk: mux: Declare u32 *table parameter as const clk: nxp: Declare mux table parameter as const u32 * clk: nxp: Remove unused variable * clk-imx: (28 commits) dt-bindings: clock: drop useless consumer example clk: imx: Select MXC_CLK for i.MX93 clock driver clk: imx: remove redundant re-assignment of pll->base MAINTAINERS: clk: imx: add git tree and dt-bindings files clk: imx: pll14xx: Support dynamic rates clk: imx: pll14xx: Add pr_fmt clk: imx: pll14xx: explicitly return lowest rate clk: imx: pll14xx: name variables after usage clk: imx: pll14xx: consolidate rate calculation clk: imx: pll14xx: Use FIELD_GET/FIELD_PREP clk: imx: pll14xx: Drop wrong shifting clk: imx: pll14xx: Use register defines consistently clk: imx8mp: remove SYS PLL 1/2 clock gates clk: imx8mn: remove SYS PLL 1/2 clock gates clk: imx8mm: remove SYS PLL 1/2 clock gates clk: imx: add i.MX93 clk clk: imx: support fracn gppll clk: imx: add i.MX93 composite clk dt-bindings: clock: add i.MX93 clock definition dt-bindings: clock: Add imx93 clock support ... * clk-rockchip: clk: rockchip: re-add rational best approximation algorithm to the fractional divider clk/rockchip: Use of_device_get_match_data() clk: rockchip: Add CLK_SET_RATE_PARENT to the HDMI reference clock on rk3568 clk: rockchip: drop CLK_SET_RATE_PARENT from dclk_vop* on rk3568 clk: rockchip: Add more PLL rates for rk3568
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Stephen Boyd authored
- Kunit tests for clk-gate implementation - Convert Cirrus Logic CS2000P driver to regmap, yamlify DT binding and add support for dynamic mode * clk-xilinx: clk: zynqmp: replace warn_once with pr_debug for failed clock ops * clk-kunit: clk: gate: Add some kunit test suites * clk-cs2000: clk: cs2000-cp: convert driver to regmap clk: cs2000-cp: freeze config during register fiddling clk: cs2000-cp: make clock skip setting configurable clk: cs2000-cp: add support for dynamic mode clk: cs2000-cp: Make aux output function controllable dt-bindings: clock: cs2000-cp: document cirrus,dynamic-mode dt-bindings: clock: cs2000-cp: document cirrus,clock-skip flag dt-bindings: clock: cs2000-cp: document aux-output-source dt-bindings: clock: convert cs2000-cp bindings to yaml * clk-renesas: dt-bindings: clock: renesas: Make example 'clocks' parsable clk: rs9: Add Renesas 9-series PCIe clock generator driver clk: fixed-factor: Introduce devm_clk_hw_register_fixed_factor_index() dt-bindings: clk: rs9: Add Renesas 9-series I2C PCIe clock generator clk: renesas: r8a779f0: Add PFC clock clk: renesas: r8a779f0: Add I2C clocks clk: renesas: r8a779f0: Add WDT clock clk: renesas: r8a779f0: Fix RSW2 clock divider clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC dt-bindings: clock: renesas: Document RZ/V2L SoC dt-bindings: clock: Add R9A07G054 CPG Clock and Reset Definitions clk: renesas: r8a779a0: Add CANFD module clock clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3 clk: renesas: r8a7799[05]: Add MLP clocks clk: renesas: r8a779f0: Add SYS-DMAC clocks
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Stephen Boyd authored
- Clock configuration on Microchip PolarFire SoCs - Free allocations on probe error in Mediatek clk driver - Modernize Mediatek clk driver by consolidating code * clk-microchip: clk: microchip: Add driver for Microchip PolarFire SoC dt-bindings: clk: microchip: Add Microchip PolarFire host binding * clk-si: clk-si5341: replace snprintf in show functions with sysfs_emit clk: si5341: fix reported clk_rate when output divider is 2 * clk-mtk: (32 commits) clk: mediatek: Warn if clk IDs are duplicated clk: mediatek: mt8195: Implement remove functions clk: mediatek: mt8195: Implement error handling in probe functions clk: mediatek: mt8195: Hook up mtk_clk_simple_remove() clk: mediatek: Unregister clks in mtk_clk_simple_probe() error path clk: mediatek: mtk: Implement error handling in register APIs clk: mediatek: pll: Implement error handling in register API clk: mediatek: mux: Implement error handling in register API clk: mediatek: mux: Reverse check for existing clk to reduce nesting level clk: mediatek: gate: Implement error handling in register API clk: mediatek: cpumux: Implement error handling in register API clk: mediatek: mtk: Clean up included headers clk: mediatek: Add mtk_clk_simple_remove() clk: mediatek: Implement mtk_clk_unregister_composites() API clk: mediatek: Implement mtk_clk_unregister_divider_clks() API clk: mediatek: Implement mtk_clk_unregister_factors() API clk: mediatek: Implement mtk_clk_unregister_fixed_clks() API clk: mediatek: pll: Clean up included headers clk: mediatek: pll: Implement unregister API clk: mediatek: pll: Split definitions into separate header file ... * clk-at91: clk: at91: clk-master: remove dead code clk: at91: sama7g5: fix parents of PDMCs' GCLK clk: at91: sama7g5: Allow MCK1 to be exported and referenced in DT clk: at91: allow setting PMC_AUDIOPINCK clock parents via DT * clk-st: clk: stm32mp1: Add parent_data to ETHRX clock clk: stm32mp1: Split ETHCK_K into separate MUX and GATE clock
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- 25 Mar, 2022 2 commits
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Krzysztof Kozlowski authored
Consumer examples in the bindings of resource providers are trivial, useless and duplication of code. Remove the example code for consumer Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Link: https://lore.kernel.org/r/20220316130858.93455-2-krzysztof.kozlowski@canonical.comAcked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Stephen Boyd <sboyd@kernel.org>
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Rob Herring authored
'clocks' in the example is not parsable with the 0 phandle value because the number of #clock-cells is unknown in the previous entry. Solve this by adding the clock provider node. Only 'cpg_clocks' is needed as the examples are built with fixups which can be used to identify phandles. This is in preparation to support schema validation on .dtb files. Signed-off-by:
Geert Uytterhoeven <geert@linux-m68k.org> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
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- 18 Mar, 2022 2 commits
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Marek Vasut authored
Add driver for Renesas 9-series PCIe clock generators. This driver is designed to support 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ series I2C PCIe clock generators, currently the only tested and supported chip is 9FGV0241. The driver is capable of configuring per-chip spread spectrum mode and output amplitude, as well as per-output slew rate. Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Stephen Boyd <sboyd@kernel.org> Cc: devicetree@vger.kernel.org Link: https://lore.kernel.org/r/20220226040723.143705-3-marex@denx.de [sboyd@kernel.org: Use non-underscore API for fixed factor] Signed-off-by:
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Marek Vasut authored
Add an API for a fixed factor clk that uses an index for the parent instead of a string name. This allows us to move drivers away from the string based method of describing parents and use the DT/firmware based method instead. Signed-off-by:
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- 15 Mar, 2022 2 commits
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Marek Vasut authored
Add binding for Renesas 9-series PCIe clock generators. This binding is designed to support 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ series I2C PCIe clock generators, currently the only tested and supported chip is 9FGV0241. Signed-off-by:
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Abel Vesa authored
Most of the i.MX clock generic API is built by selecting MXC_CLK. Without it, the i.MX93 clock driver will fail to build: aarch64-linux-gnu-ld: drivers/clk/imx/clk-imx93.o: in function `imx93_clocks_probe': clk-imx93.c:(.text+0xa8): undefined reference to `imx_obtain_fixed_clk_hw' So fix this by selecting MXC_CLK for the CLK_IMX93. Fixes: 24defbe1 ("clk: imx: add i.MX93 clk") Signed-off-by:
Abel Vesa <abel.vesa@nxp.com> Reported-by:
kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/r/20220315082446.3120850-1-abel.vesa@nxp.comReviewed-by:
Peng Fan <peng.fan@nxp.com> Signed-off-by:
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- 12 Mar, 2022 1 commit
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Daire McNamara authored
Add support for clock configuration on Microchip PolarFire SoC Reviewed-by:
Padmarao Begari <padmarao.begari@microchip.com> Signed-off-by:
Daire McNamara <daire.mcnamara@microchip.com> Co-developed-by:
Conor Dooley <conor.dooley@microchip.com> Signed-off-by:
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- 09 Mar, 2022 6 commits
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Stephen Boyd authored
Merge tag 'renesas-clk-for-v5.18-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Add watchdog (WDT), I2C, and pin function controller (PFC) clocks on R-Car S4-8 - A small fix * tag 'renesas-clk-for-v5.18-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a779f0: Add PFC clock clk: renesas: r8a779f0: Add I2C clocks clk: renesas: r8a779f0: Add WDT clock clk: renesas: r8a779f0: Fix RSW2 clock divider
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Stephen Boyd authored
Merge tag 'v5.18-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip Pull Rockchip clk driver updates from Heiko Stuebner: - Improve the clocks for the rk3568 display outputs (parenting, pll-rates) - Use of_device_get_match_data() instead of open-coding on rk3568 - Reintroduce the expected fractional-divider behaviour that disappeared with the addition of CLK_FRAC_DIVIDER_POWER_OF_TWO_PS * tag 'v5.18-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: re-add rational best approximation algorithm to the fractional divider clk/rockchip: Use of_device_get_match_data() clk: rockchip: Add CLK_SET_RATE_PARENT to the HDMI reference clock on rk3568 clk: rockchip: drop CLK_SET_RATE_PARENT from dclk_vop* on rk3568 clk: rockchip: Add more PLL rates for rk3568
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Colin Ian King authored
There are two identical assignments of pll->base to the same value, the second assignment is redundant and can be removed. Cleans up cppcheck warning: drivers/clk/imx/clk-sscg-pll.c:528:12: style: Variable 'pll->base' is reassigned a value before the old one has been used. [redundantAssignment] Signed-off-by:
Colin Ian King <colin.i.king@gmail.com> Link: https://lore.kernel.org/r/20220303090508.1125175-1-colin.i.king@gmail.comSigned-off-by:
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Abel Vesa authored
The i.MX clocks dt-bindings are going through the same tree as the drivers, so add them to the same entry. Also add the git tree and branch used. Signed-off-by:
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Stephen Boyd authored
Merge tag 'clk-imx-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx Pull i.MX clk driver updates from Abel Vesa: - Add i.MXRT1050 clock driver and bindings - Add i.MX8DXL clock driver and bindings - Add i.MX93 clock driver and bindings - Remove SYS PLL 1/2 clock gates for i.MX8M* - Remove AUDIO MCLK ROOT from i.MX7D - Add fracn gppll clock type used by i.MX93 - Add new composite clock for i.MX93 - Add missing media mipi phy ref clock for i.MX8MP - Fix off by one in imx_lpcg_parse_clks_from_dt - Rework for the pll14xx * tag 'clk-imx-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux: (24 commits) clk: imx: pll14xx: Support dynamic rates clk: imx: pll14xx: Add pr_fmt clk: imx: pll14xx: explicitly return lowest rate clk: imx: pll14xx: name variables after usage clk: imx: pll14xx: consolidate rate calculation clk: imx: pll14xx: Use FIELD_GET/FIELD_PREP clk: imx: pll14xx: Drop wrong shifting clk: imx: pll14xx: Use register defines consistently clk: imx8mp: remove SYS PLL 1/2 clock gates clk: imx8mn: remove SYS PLL 1/2 clock gates clk: imx8mm: remove SYS PLL 1/2 clock gates clk: imx: add i.MX93 clk clk: imx: support fracn gppll clk: imx: add i.MX93 composite clk dt-bindings: clock: add i.MX93 clock definition dt-bindings: clock: Add imx93 clock support clk: imx: off by one in imx_lpcg_parse_clks_from_dt() dt-bindings: fsl: scu: add imx8dxl scu clock support clk: imx7d: Remove audio_mclk_root_clk clk: imx8mp: Add missing IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT clock ...
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git://git.kernel.org/pub/scm/linux/kernel/git/at91/linuxStephen Boyd authored
Pull AT91 clk driver changes From Nicolas Ferre: - sama7g5: One low priority fix for GCLK of PDMC - clk-master: cleanup of dead code * tag 'clk-at91-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: clk: at91: clk-master: remove dead code clk: at91: sama7g5: fix parents of PDMCs' GCLK
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- 08 Mar, 2022 2 commits
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Claudiu Beznea authored
Commit facb87ad ("clk: at91: sama7g5: remove prescaler part of master clock") removed the master clock's prescaler from clock tree of SAMA7G5 as it has been discovered that there is a hardware bug when trying to change it at run-time (bug is described in description of commit facb87ad ("clk: at91: sama7g5: remove prescaler part of master clock")). This was previously changed at CPUFreq driver request. Thus, with commit facb87ad ("clk: at91: sama7g5: remove prescaler part of master clock") there is no need of code that handles run-time changes of master clock's prescaler, thus remove this code. Signed-off-by:
Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by:
Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20220203110202.18329-1-claudiu.beznea@microchip.com
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Codrin Ciubotariu authored
Audio PLL can be used as parent by the GCLKs of PDMCs. Fixes: cb783bbb ("clk: at91: sama7g5: add clock support for sama7g5") Signed-off-by:
Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Reviewed-by:
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- 04 Mar, 2022 19 commits
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Sascha Hauer authored
The pll1443x PLL so far only supports rates from a rate table passed during initialization. Calculating PLL settings dynamically helps audio applications to get their desired rates, so support for this is added in this patch. The strategy to get to the PLL setting for a rate is: - First try to only adjust kdiv which specifies the fractional part of the PLL. This setting can be changed without glitches on the output and is therefore preferred - When that isn't possible then the rate table is searched for suitable rates, so for standard rates the same settings are used as without this patch - As a last resort the best settings are calculated dynamically The code in this patch is based on patches from Adrian Alonso <adrian.alonso@nxp.com> and Mads Bligaard Nielsen <bli@bang-olufsen.dk> Signed-off-by:
Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by:
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Sascha Hauer authored
Print all messages from within the pll14xx driver with a common prefix using pr_fmt. No need to print function names anymore, so drop them from the messages. Signed-off-by:
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Sascha Hauer authored
clk_pll14xx_round_rate() returns the lowest rate by indexing into the rate table with the variable i. i is actually pll->rate_count as this is the value we come out of the loop with. Use pll->rate_count explicitly to make it a bit more clear what is being done. While at it fix a typo in the comment. No functional change. Signed-off-by:
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Sascha Hauer authored
In clk_pll1443x_set_rate() 'tmp' is used for the content of different registers which makes it a bit hard to follow. Use different variables named after the registers to make it clearer. No functional change intended. Signed-off-by:
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Sascha Hauer authored
The PLL driver has support for two different PLLs: The pll1416x and the pll1443x. The latter has support for an additional kdiv value. recalc_rate can be the same calculation when kdiv is assumed to be zero for the PLL which doesn't support that value. Signed-off-by:
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Sascha Hauer authored
Linux has these marvelous FIELD_GET/FIELD_PREP macros for easy access to bitfields in registers. Use them and remove the now unused *_SHIFT defines. Signed-off-by:
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Sascha Hauer authored
The code tries to mask the bits in SDIV_MASK from 'tmp'. SDIV_MASK already contains the shifted value, so shifting it again is wrong. No functional change though as SDIV_SHIFT is zero. Signed-off-by:
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Sascha Hauer authored
The driver has defines for the registers, but they are mostly unused. Use the defines consistently throughout the driver. While at it rename DIV_CTL to DIV_CTL0 because that's the name in the reference manual. Signed-off-by:
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Peng Fan authored
Remove the PLL 1/2 gates as it make AMP clock management harder without obvious benifit. Signed-off-by:
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Peng Fan authored
Remove the PLL 1/2 gates as it make AMP clock management harder without obvious benifit. Signed-off-by:
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Peng Fan authored
Remove the PLL 1/2 gates as it make AMP clock management harder without obvious benifit. Signed-off-by:
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Peng Fan authored
Add i.MX93 clk driver. i.MX93 clk hardware design is different compared with i.MX8M. It supports 4 sources for each clk root and the sources are separated into a few groups, low speed/fast io/audio and etc. Reviewed-by:
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Peng Fan authored
This PLL module is a Fractional-N synthesizer, supporting 30-bit numerator and denominator. Numerator is a signed number. It has feature to adjust fractional portion of feedback divider dynamically. This fracn gppll is used in i.MX93. Reviewed-by:
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Peng Fan authored
i.MX93 CCM ROOT clock has a mux, gate and divider in one register, here is to combine all these into one composite clk and simplify clk tree. i.MX93 CCM is a new IP compared with i.MX8M, so introduce a new file. Reviewed-by:
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Peng Fan authored
Add i.MX93 clock definition Reviewed-by:
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Peng Fan authored
Add the clock dt-binding file for i.MX93. Reviewed-by:
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Dan Carpenter authored
The > needs to be >= to prevent an off by one access. Fixes: d5f1e6a2 ("clk: imx: imx8qxp-lpcg: add parsing clocks from device tree") Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
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Abel Vesa authored
Add imx8dxl scu clock support. Signed-off-by:
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Abel Vesa authored
The audio_mclk_root_clk was added as a gate with the CCGR121 (0x4790), but according to the reference manual, there is no such gate. The CCGR121 belongs to ECSPI2 and it is not shared. Fixes: 8f6d8094 ("ARM: imx: add imx7d clk tree support") Reported-by:
David Wolfe <david.wolfe@nxp.com> Signed-off-by:
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- 26 Feb, 2022 3 commits
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Stephen Boyd authored
Clarify that the 'target' clk isn't being modified, instead it's being searched for. Mark it const so the function can't modify it. Signed-off-by:
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Stephen Boyd authored
This list array doesn't change at runtime. Mark it const to move to RO memory. Signed-off-by:
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Jonathan Neuschäfer authored
Now that clk_register_mux_table takes a const u32 *, we can declare the mux table as const u32[]. Signed-off-by:
Jonathan Neuschäfer <j.neuschaefer@gmx.net> Link: https://lore.kernel.org/r/20220205103613.1216218-8-j.neuschaefer@gmx.netSigned-off-by:
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