1. 13 Dec, 2016 6 commits
    • Rajneesh Bhardwaj's avatar
      platform/x86: intel_pmc_core: Add LTR IGNORE debug feature · 9c2ee199
      Rajneesh Bhardwaj authored
      SPT LTR_IGN register provides a means to make the PMC ignore the LTR values
      reported by the individual PCH devices.
      
      echo <IP Offset> > /sys/kernel/debug/pmc_core/ltr_ignore.
      
      When a particular IP Offset bit is set the PMC will ignore the LTR value
      reported by the corresponding IP when the PMC performs the latency
      coalescing.
      
      IP Offset	IP Name
      0		SPA
      1		SPB
      2		SATA
      3		GBE
      4		XHCI
      5		RSVD
      6		ME
      7		EVA
      8		SPC
      9		Azalia/ADSP
      10		RSVD
      11		LPSS
      12		SPD
      13		SPE
      14		Camera
      15		ESPI
      16		SCC
      17		ISH
      Signed-off-by: default avatarRajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
      [dvhart: pmc_core_ltr_ignore_write local declaration order cleanup]
      Signed-off-by: default avatarDarren Hart <dvhart@linux.intel.com>
      9c2ee199
    • Rajneesh Bhardwaj's avatar
      platform/x86: intel_pmc_core: Add MPHY PLL clock gating status · fe748227
      Rajneesh Bhardwaj authored
      ModPhy Common lanes can provide the clock gating status for the important
      system PLLs such as Gen2 USB3PCIE2 PLL, DMIPCIE3 PLL, SATA PLL and MIPI
      PLL.
      
      On SPT, in addition to the crystal oscillator clock, the 100Mhz Gen2
      USB3PCI2 PLL clock is used as the PLL reference clock and Gen2 PLL idling
      is a necessary condition for the platform to go into low power states like
      PC10 and S0ix.
      Signed-off-by: default avatarRajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
      Signed-off-by: default avatarDarren Hart <dvhart@linux.intel.com>
      fe748227
    • Rajneesh Bhardwaj's avatar
      platform/x86: intel_pmc_core: ModPhy core lanes pg status · 173943b3
      Rajneesh Bhardwaj authored
      The PCH implements a number of High Speed I/O (HSIO) lanes that are split
      between PCIe*, USB 3.0, SATA, GbE, USB OTG and SSIC. This patch shows the
      current power gating status of the available ModPhy Core lanes. This is
      done by sending a message to the PMC (MTPMC) that contains the XRAM
      register offset for the MPHY_CORE_STS_0 and MPHY_CORE_STS_1 and then by
      reading the response sent by the PMC (MFPMC).
      
      While enabling low power modes we often encounter situations when the
      ModPhy lanes are not power gated and it becomes hard to debug which lane is
      active and which is not in the absence of an external hardware debugger
      (JTAG/ITP). This patch eliminates the dependency on an external hardware
      debugger for reading the ModPhy Lanes power gating status.
      
      This patch requires PMC_READ_DISABLE setting to be disabled in the platform
      bios.
      
      cat /sys/kernel/debug/pmc_core/mphy_lanes_power_gating_status
      Signed-off-by: default avatarRajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
      Signed-off-by: default avatarDarren Hart <dvhart@linux.intel.com>
      173943b3
    • Rajneesh Bhardwaj's avatar
      platform/x86: intel_pmc_core: Add PCH IP Power Gating Status · 0bdfaf42
      Rajneesh Bhardwaj authored
      This patch adds the support for reading the power gating status of various
      devices present on Sunrise Point PCH. This is intended to be used for
      debugging purpose while tuning the platform for power optimizations and
      also to understand which devices (on PCH) are blocking the system to enter
      a low power state.
      
      Power Management Controller on Sunrise Point PCH provides access to "PGD
      PFET Enable Ack Status Registers (ppfear)". This patch reads and decodes
      this register and dumps the output in formatted manner showing various
      devices present on the PCH and their "Power Gating" status.
      
      Further documentation can be found in Intel 7th Gen Core family mobile u/y
      processor io datasheet volume 2.
      
      Sample output (stripped and not in order):
      
      cat /sys/kernel/debug/pmc_core/pch_ip_power_gating_status
      PMC				State: Not Power gated
      OPI-DMI				State: Not Power gated
      XHCI				State: Power gated
      LPSS				State: Power gated
      CSME_PSF			State: Not power gated
      Signed-off-by: default avatarRajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
      Signed-off-by: default avatarDarren Hart <dvhart@linux.intel.com>
      0bdfaf42
    • Rajneesh Bhardwaj's avatar
      platform/x86: intel_pmc_core: Fix PWRMBASE mask and mmio reg len · 8434709b
      Rajneesh Bhardwaj authored
      On Sunrise Point PCH, the Power Management Controller provides 4K bytes of
      memory space for various power management and debug registers. This fix is
      needed to access power management & debug registers that are mapped at a
      higher offset.
      
      Also, this provides a fix for correctly masking the PWRMBASE as the initial
      bits (0-11) are reserved.
      Signed-off-by: default avatarRajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
      Signed-off-by: default avatarDarren Hart <dvhart@linux.intel.com>
      8434709b
    • Lee, Chun-Yi's avatar
      platform/x86: acer-wmi: Only supports AMW0_GUID1 on acer family · 5241b193
      Lee, Chun-Yi authored
      The AMW0_GUID1 wmi is not only found on Acer family but also other
      machines like Lenovo, Fujitsu and Medion. In the past, acer-wmi handled
      those non-Acer machines by quirks list.
      
      But actually acer-wmi driver was loaded on any machine that had
      AMW0_GUID1. This behavior is strange because those machines should be
      supported by appropriate wmi drivers. e.g. fujitsu-laptop,
      ideapad-laptop.
      
      This patch adds the logic to check the machine that has AMW0_GUID1
      should be in Acer/Packard Bell/Gateway white list. But, it still keeps
      the quirk list of those supported non-acer machines for backward
      compatibility.
      Tested-by: default avatarBjørn Mork <bjorn@mork.no>
      Signed-off-by: default avatarLee, Chun-Yi <jlee@suse.com>
      Signed-off-by: default avatarDarren Hart <dvhart@linux.intel.com>
      5241b193
  2. 23 Oct, 2016 1 commit
    • Vadim Pasternak's avatar
      platform/x86: Introduce support for Mellanox hotplug driver · 30488704
      Vadim Pasternak authored
      Enable system support for the Mellanox Technologies hotplug platform
      driver, which provides support for the next Mellanox basic systems:
      "msx6710", "msx6720", "msb7700", "msn2700", "msx1410", "msn2410",
      "msb7800", "msn2740", "msn2100" and also various number of derivative
      systems from the above basic types.
      This driver handles hot-plug events for the power suppliers, power
      cables and fans for the above systems.
      
      The Kconfig currently controlling compilation of this code is:
      driver/platform/x86:config MLX_CPLD_PLATFORM
                             tristate "Mellanox platform hotplug driver support"
      Signed-off-by: default avatarVadim Pasternak <vadimp@mellanox.com>
      Signed-off-by: default avatarDarren Hart <dvhart@linux.intel.com>
      30488704
  3. 19 Oct, 2016 15 commits
  4. 18 Oct, 2016 18 commits