SCPSYS driver misses the module.h include which makes it fail
when compiling with allmodconf.

This patch fixes this.
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Olof Johansson <olof@lixom.net>

mvebu soc changes for v4.3 (part #1)

- Extend suspend to RAM support in order to add new mvebu SoC
- Add standby support for all Armada 3xx/XP SoCs

* tag 'mvebu-soc-4.3-1' of git://git.infradead.org/linux-mvebu:
  ARM: mvebu: Warn about the wake-up sources not taken into account in suspend
  ARM: mvebu: Add standby support
  ARM: mvebu: Use __init for the PM initialization functions
  ARM: mvebu: prepare pm-board.c for the introduction of Armada 38x support
  ARM: mvebu: prepare mvebu_pm_store_bootinfo() to support multiple SoCs
  ARM: mvebu: do not check machine in mvebu_pm_init()
  ARM: mvebu: prepare set_cpu_coherent() for future extension
Signed-off-by: Olof Johansson <olof@lixom.net>

arm: Xilinx Zynq SoC patches for v4.2

- Fix earlyprintk, jump trampoline for SMP
- Update git tree location
- Setup PL310 aux (bit 22)

* tag 'zynq-soc-for-4.3' of https://github.com/Xilinx/linux-xlnx:
  ARM: zynq: reserve space for jump target in secondary trampoline
  clk: zynq: remove redundant $(CONFIG_ARCH_ZYNQ) in Makefile
  MAINTAINERS: Update Zynq git tree location
  ARM: zynq: Set bit 22 in PL310 AuxCtrl register (6395/1)
  ARM: zynq: Fix earlyprintk in big endian mode
Signed-off-by: Olof Johansson <olof@lixom.net>

Add Kconfig entries, header file changes and addition to the documentation.
The early debug infrastructure is also added for easy development.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Olof Johansson <olof@lixom.net>

Add a zero argument to the .word directive in
zynq_secondary_trampoline.  Without an expression the assembler emits
nothing for the .word directive.

This makes it so that the intended range is communicated to ioremap
and outer_flush_range in zynq_cpun_start; e.g. for LE
trampoline_code_size evaluates to 12 now instead of 8.

Found by inspection.  I'm not aware of any real problem this fixes.
Tested by doing on online/offline loop on ZC702.
Signed-off-by: Nathan Lynch <nathan_lynch@mentor.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Kbuild descends into drivers/clk/zynq/ only when CONFIG_ARCH_ZYNQ
is enabled.  (see drivers/clk/Makefile)

$(CONFIG_ARCH_ZYNQ) in drivers/clk/zynq/Makefile always evaluates
to 'y'.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

The git tree for Zynq moved to Github. Update the MAINTAINERS record to
reflect the change.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Add power domains for ZX296702 to power off
inactive power domains in runtime.
Signed-off-by: Jun Nie <jun.nie@linaro.org>
[olof: Marked zx296702_pd_driver as __initdata to avoid section mismatch]
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'socfpga_updates_for_v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/soc

SoCFPGA updates for v4.3
- Add smp.ops.cpu_kill() for kexec
- Add reboot capability for Arria10

* tag 'socfpga_updates_for_v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  ARM: socfpga: add reset for the Arria 10 platform
  ARM: socfpga: add smp_ops.cpu_kill to make kexec/kdump available
Signed-off-by: Olof Johansson <olof@lixom.net>

- ARM: mediatek: Add regmap to mediatek Kconfig
- soc: mediatek: Drop owner assignment from platform_driver
- soc: Mediatek: Add SCPSYS power domain driver
- dt-bindings: soc: Add documentation for the MediaTek SCPSYS unit
- soc: mediatek: Add infracfg misc driver support

* tag 'v4.2-next-soc' of https://github.com/mbgg/linux-mediatek:
  ARM: mediatek: Add regmap to mediatek Kconfig
  soc: mediatek: Drop owner assignment from platform_driver
  soc: Mediatek: Add SCPSYS power domain driver
  dt-bindings: soc: Add documentation for the MediaTek SCPSYS unit
  soc: mediatek: Add infracfg misc driver support
Signed-off-by: Olof Johansson <olof@lixom.net>

On the Armada 370/XP/38x/39x SoCs when the suspend to ram feature is
supported, the SoCs are shutdown and will be woken up by an external
micro-controller, so there is no possibility to setup wake-up sources
from Linux. However, in standby mode, the SoCs stay powered and it is
possible to wake-up from any interrupt sources. Since when the users
configures the enabled wake-up sources there is no way to know if the
user will be doing suspend to RAM or standby, we just allow all
wake-up sources to be enabled, and only warn when entering suspend to
RAM

The purpose of this patch is to inform the user that in suspend to ram
mode, the wake-up sources won't be taken into consideration.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

This clarifies the location of the files maintained by me.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>

This is the pxa changes for v4.3 cycle.

There is mostly one evolution on the dma side, to enable cooperation
of the legacy pxa DMA API, and the new dmaengine API.
Once all drivers using DMA are converted, the legacy DMA API should
be removed.

* tag 'pxa-for-4.3-v2' of https://github.com/rjarzmik/linux:
  ARM: pxa: Use setup_timer
  ARM: pxa: Use module_platform_driver
  ARM: pxa: transition to dmaengine phase 1
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'omap-for-v4.3/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc

SoC changes for omaps for v4.3 merge window:

- Clean-up omap4_local_timer_init to drop deal legacy code

- Provide proper IO map table for dra7

- Clean-up IOMMU layer init code as it now uses IOMMU framework

- A series of changes to fix up dm814x support that's been in a broken
  half-merged state for quite some time

- A series of PRCM and hwmod changes via Paul Walmsley <paul@pwsan.com>:

  - I/O wakeup support for AM43xx
  - register lock and unlock support to the hwmod code (needed for the RTC
    IP blocks on some chips)
  - several fixes for sparse warnings and an unnecessary null pointer test
  - a DRA7xx clockdomain configuration workaround, to deal with some hardware
    bugs

* tag 'omap-for-v4.3/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (21 commits)
  ARM: OMAP2: Add minimal dm814x hwmod support
  ARM: OMAP2+: Prepare dm81xx hwmod code for adding minimal dm814x support
  ARM: PRM: AM437x: Enable IO wakeup feature
  ARM: OMAP4+: PRM: Add AM437x specific data
  ARM: OMAP: PRM: Remove hardcoding of IRQENABLE_MPU_2 and IRQSTATUS_MPU_2 register offsets
  ARM: dts: AM4372: Add PRCM IRQ entry
  ARM: AM43xx: Add the PRM IRQ register offsets
  ARM: OMAP4: PRM: Remove hardcoding of PRM_IO_PMCTRL_OFFSET register
  ARM: OMAP2+: Add support for initializing dm814x clocks
  ARM: OMAP2+: Add custom prwdm_operations for 81xx to support dm814x
  ARM: OMAP2+: Add minimal clockdomains for dm814x
  ARM: OMAP2+: Fix scm compatible for dm814x
  ARM: OMAP2+: Fix dm814x DT_MACHINE_START
  ARM: OMAP2+: Remove module references from IOMMU machine layer
  ARM: DRA7: Provide proper IO map table
  ARM: OMAP2+: Clean up omap4_local_timer_init
  ARM: OMAP2: Delete an unnecessary check
  ARM: OMAP2+: sparse: add missing function declarations
  ARM: OMAP2+: sparse: add missing static declaration
  ARM: OMAP2+: hwmod: add support for lock and unlock hooks
  ...
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'renesas-soc-for-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc

Renesas ARM Based SoC Updates for v4.3

* Add basic support for gose/r8a7793

* tag 'renesas-soc-for-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: gose: enable R-Car Gen2 regulator quirk
  ARM: shmobile: Basic r8a7793 SoC support
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'sti-soc-for-v4.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/sti into next/soc

STi SoC updates for v4.3, round 1.

Highlights:
-----------
 - Add code to release secondary cores from holding pen.
 - Remove useless call to trace_hardirqs_off() in secondary core init function.

* tag 'sti-soc-for-v4.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/sti:
  ARM: STi: Remove platform call to trace_hardirqs_off()
  ARM: STi: Add code to release secondary cores from holding pen.
Signed-off-by: Olof Johansson <olof@lixom.net>

Until now only one Armada XP and one Armada 388 based board supported
suspend to ram. However, most of the recent mvebu SoCs can support the
standby mode. Unlike for the suspend to ram, nothing special has to be
done for these SoCs. This patch allows the system to use the standby
mode on Armada 370, 38x, 39x and XP SoCs. There are issues with the
Armada 375, and the support might be added (if possible) in a future
patch.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

mvebu_pm_init and mvebu_armada_pm_init are only called during boot, so
flag them with __init and save some memory.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

The pm-board.c code contains the board-specific logic to enter suspend
to RAM. Until now, the code supported only the Armada XP GP board, so
all functions and symbols were named with armada_xp_gp. However, it
turns out that the Armada 388 GP also uses the same 3 GPIOs protocol
to talk to the PIC microcontroller that controls the power supply.

Since we are going to re-use the same code with no change for Armada
38x, this commit renames the functions and symbols to use just
"armada" instead of "armada_xp_gp". Better names can be found if one
day other boards having a different protocol/mechanism are supported
in the kernel.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

As we are going to introduce support for Armada 38x in pm.c, split out
the Armada XP part of mvebu_pm_store_bootinfo() into
mvebu_pm_store_armadaxp_bootinfo(), and make the former retunr an
error when an unsupported SoC is used.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

The mvebu_pm_init() initializes the support for suspend/resume, and
before doing that, it checks if we are on a board on which
suspend/resume is actually supported. However, this check is already
done by mvebu_armada_xp_gp_pm_init(), and there is no need to
duplicate the check: callers of mvebu_pm_init() should now what they
are doing.

This commit is done in preparation to the addition of suspend/resume
support on Armada 38x.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

This patch prepares the set_cpu_coherent() function in coherency.c to
be extended to support other SoCs than Armada XP. It will be needed on
Armada 38x to re-enable the coherency after exiting from suspend to
RAM.

This preparation simply moves the function further down in coherency.c
so that it can use coherency_type(), and uses that function to only do
the Armada XP specific work if we are on Armada XP.
Signed-off-by: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Update dm814x changes for sparse fixes to make data structures
static.

Conflicts:
	arch/arm/mach-omap2/omap_hwmod_81xx_data.c

Let's add minimal set of dm814x hwmods to have a bootable system.

Cc: Matthijs van Duin <matthijsvanduin@gmail.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

Let's change the defines so we can share the hwmod code better between
dm816x and dm814x, and let's add the dm814x specific defines. And let's
rename the shared ones to start with dm81xx. No functional changes.

Cc: Matthijs van Duin <matthijsvanduin@gmail.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

Merge tag 'for-v4.3/omap-hwmod-prcm-a' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v4.3/soc

ARM: OMAP2+: PRCM and hwmod changes for v4.3

This series adds:

- I/O wakeup support for AM43xx
- register lock and unlock support to the hwmod code (needed for the RTC
  IP blocks on some chips)
- several fixes for sparse warnings and an unnecessary null pointer test
- a DRA7xx clockdomain configuration workaround, to deal with some hardware
  bugs

Basic build, boot, and PM tests are here:

http://www.pwsan.com/omap/testlogs/hwmod-prcm-for-v4.3/20150723080012/

Since I do not have an AM43xx or DRA7xx device, I can't test on those
platforms.

Mediatek SoC needs the regmap/syscon infrastructure.
The infrastructure is used by the clock and pinctrl driver.
This patch adds MD_SYSCON to Kconfig for all Mediatek devices.
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

Enable IO wakeup feature. This enables am437x pads to generate daisy
chained wake ups(eventually generates aprcm Interrupt) especially
when in low power modes.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>

The register offsets for some of the PRM Registers are different
hence populating the differing fields. This is needed to support
IO wake up feature for am437x family.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>

The register offsets of IRQENABLE_MPU_2 and IRQSTATUS_MPU_2 are hardcoded.
This makes it difficult to reuse the code for SoCs like AM437x that have
a single instance of IRQENABLE_MPU and IRQSTATUS_MPU registers.
Hence handling the case using offset of 4 to accommodate single set of IRQ*
registers generically.
Signed-off-by: Keerthy <j-keerthy@ti.com>
[paul@pwsan.com: fixed whitespace alignment problems reported by checkpatch.pl]
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>

Add PRCM IRQ entry.  This is needed for I/O wakeup support.
Signed-off-by: Keerthy <j-keerthy@ti.com>
[paul@pwsan.com: added I/O wakeup note in commit description]
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>

Add the PRM IRQ register offsets.  This is needed to support PRM I/O
wakeup on AM43xx.
Signed-off-by: Keerthy <j-keerthy@ti.com>
[paul@pwsan.com: improved patch description, moved the PRM_IO_PMCTRL macro
 out of the CM section]
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>

PRM_IO_PMCTRL_OFFSET need not be same for all SOCs hence
remove hardcoding and use the value provided by the omap_prcm_irq_setup
structure. This is done to support IO wakeup on am437x series.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>

Calling trace_hardirqs_off() from the platform specific
secondary startup code as not been necessary since Dec 2010
when Russell King consolidated the call into the common SMP
code.

2c0136db ARM: SMP: consolidate trace_hardirqs_off() into common SMP code
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>

Most upstream devs boot STi platform via JTAG which abuses the
boot process by setting the PC of secondary cores directly. As
a consquence, booting STi platforms via u-boot results in only
the primary core being brought up as the code to manage the
holding pen is not upstream.

This patch adds the necessary code to bring the secondary cores
out of the holding pen. It uses the cpu-release-addr DT property
to get the address of the holding pen from the bootloader.

With this patch booting upstream kernels via u-boot works
correctly:

[    0.045456] CPU: Testing write buffer coherency: ok
[    0.045597] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[    0.045734] Setting up static identity map for 0x40209000 - 0x40209098
[    0.065047] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[    0.065081] Brought up 2 CPUs
[    0.065089] SMP: Total of 2 processors activated (5983.43 BogoMIPS).
[    0.065092] CPU: All CPU(s) started in SVC mode.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>

This patch is based on the
commit 1a8e41cd ("ARM: 6395/1: VExpress: Set bit 22 in the PL310
(cache controller) AuxCtlr register")

Clearing bit 22 in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.

Coherent DMA buffers in Linux always have a cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.

For Zynq, this fix avoids memory inconsistencies between Gigabit
Ethernet controller (GEM) and CPU when DMA_CMA is disabled.
Suggested-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Signed-off-by: Thomas Betker <thomas.betker@rohde-schwarz.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

earlyprintk messages are not appearing on the terminal
emulator during a big endian kernel boot. In BE mode
sending full words to UART will result in unprintable
characters as they are byte swapped versions of printable
ones. So send only bytes.
Signed-off-by: Arun Chandran <achandran@mvista.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Since the Arria10's reset register offset is different from the Cyclone/Arria 5,
it's best to add a new DT_MACHINE_START() for the Arria10.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v2: use altera_a10_dt_match for the A10 machine desc

Use the timer API function setup_timer instead of structure field
assignments to initialize a timer.

A simplified version of the Coccinelle semantic patch that performs
this transformation is as follows:

@change@
expression e1, e2, a;
@@

-init_timer(&e1);
+setup_timer(&e1, a, 0UL);
... when != a = e2
-e1.function = a;
Signed-off-by: Vaishali Thakkar <vthakkar1994@gmail.com>
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>