- 26 Sep, 2017 39 commits
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Evan Quan authored
Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Evan Quan authored
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Monk Liu authored
GPU reset will require all hw doing hw_init thus ucode_init_bo will be invoked again, which lead to memory leak skip the fw_buf allocation during sriov gpu reset to avoid memory leak. Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Monk Liu authored
otherwise a gpu hang will make application couldn't be killed under timedout=0 mode v2: Fix memoryleak job/job->s_fence issue unlock mn remove the ERROR msg after waiting being interrupted Signed-off-by:
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Monk Liu authored
RLC need CSB registers initiated under SRIOV during world switch otherwise the clear state buffer behav will not be recovered to current VF scheme after switch back Signed-off-by:
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Horace Chen authored
increase timeout to 12 seconds,because there may have multiple FLR waiting for done, the waiting time of events may be long, increase to 12s to reduce timeout failure. Signed-off-by:
Horace Chen <horace.chen@amd.com> Acked-by:
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Monk Liu authored
bo_free on csa is too late to put in amdgpu_fini because that time ttm is already finished, Move it earlier to avoid the page fault. Signed-off-by:
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Monk Liu authored
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Monk Liu authored
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Monk Liu authored
FRAME_CONTROL(begin) is needed for vega10 due to ucode logic change, it can fix some CTS random fail under gfx preemption enabled mode. Signed-off-by:
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Monk Liu authored
At least for SRIOV we found reload PSP fw during gpu reset cause PSP hang. Signed-off-by:
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Monk Liu authored
currently in_reset is only used in sriov gpu reset, and it will be used for other non-gfx hw component later, like PSP, so move it from gfx to adev and rename to in_sriov_reset make more sense. Signed-off-by:
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Monk Liu authored
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Monk Liu authored
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Ken Wang authored
V2 Signed-off-by:
Ken Wang <Ken.Wang@amd.com> Reviewed-by:
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Tom St Denis authored
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Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Tom St Denis authored
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Tom St Denis authored
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Tom St Denis authored
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Rex Zhu authored
fix checkpatch.pl WARNING: Prefer 'unsigned int' to bare use of 'unsigned' Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Leo Liu authored
Requested by SRIOV, the clearance of the bit moved into firmware Signed-off-by:
Leo Liu <leo.liu@amd.com> Acked-by:
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Xiangliang.Yu authored
Port it from sdma4 for wptr polling usage. Signed-off-by:
Xiangliang.Yu <Xiangliang.Yu@amd.com> Reviewed-by:
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Xiangliang.Yu authored
When hypervisor triggering FLR for one of VFs, need to enable sdma wptr polling to avoid missing wptr update if enabling doorbell. Signed-off-by:
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Christian König authored
Remove unused defines and variables. Also stop computing the gfp_flags when they aren't used. No intended functional change. Signed-off-by:
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Felix Kuehling authored
IH tracks pending retry faults in a hash table for fast lookup in interrupt context. Each VM has a short FIFO of pending VM faults for processing in a bottom half. The IH prescreening stage adds retry faults and filters out repeated retry interrupts to minimize the impact of interrupt storms. It's the VM's responsibility remove pending faults once they are handled. For now this is only done when the VM is destroyed. v2: - Made the hash table smaller and the FIFO longer. I never want the FIFO to fill up, because that would make prescreen take longer. 128 pending page faults should be enough to keep migrations busy. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Christian König <christian.koenig@amd.com> (v1) Reviewed-by:
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Felix Kuehling authored
This adds a statically sized closed hash table implementation with low memory and CPU overhead. The API is inspired by kfifo. Storing, retrieving and deleting data does not involve any dynamic memory management, which makes it ideal for use in interrupt context. Static memory usage per entry comprises a 32 or 64 bit hash key, two bits for occupancy tracking and the value size stored in the table. No list heads or pointers are needed. Therefore this data structure should be quite cache-friendly, too. It uses linear probing and lazy deletion. During lookups free space is reclaimed and entries relocated to speed up future lookups. v2: squash in do_div and _BITOPS_LONG_SHIFT fixes Signed-off-by:
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Felix Kuehling authored
To filter out high-frequency interrupts that can be safely ignored. v2: squash in trivial typo fix for si (Alex) Signed-off-by:
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Felix Kuehling authored
Signed-off-by:
Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by:
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Felix Kuehling authored
PASID management is moving into KGD. Limiting the PASID range to the number of doorbell pages is no longer practical. Signed-off-by:
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Felix Kuehling authored
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Felix Kuehling authored
Allows assigning a PASID to a VM for identifying VMs involved in page faults. The global PASID manager is also exported in the KFD interface so that AMDGPU and KFD can share the PASID space. PASIDs of different sizes can be requested. On APUs, the PASID size is deterined by the capabilities of the IOMMU. So KFD must be able to allocate PASIDs in a smaller range. Signed-off-by:
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Felix Kuehling authored
Make sure vm->root.bo is not left reserved if amdgpu_bo_kmap fails. Signed-off-by:
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Rex Zhu authored
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Rex Zhu authored
currently, for CI asics, use dpm by default, amdgpu.dpm=-1. when set amdgpu.dpm=1, enable powplay. when set amdgpu.dpm=0, disable both dpm and powerplay. when powerplay is stable on CI asics, ci_dpm will be removed. Reviewed-by:
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Rex Zhu authored
Add support for CI asics (Bonaire, Hawaii) to the powerplay hwmgr Reviewed-by:
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Rex Zhu authored
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Rex Zhu authored
Use pr_debug to prevent spamming unimportant dmesg. Reviewed-by:
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Rex Zhu authored
ConfigurableTDP do not exist from Fiji. so only use in previous ASIC. Reviewed-by:
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Rex Zhu authored
This ports support for CI asics (Bonaire, Hawaii) to the powerplay smumgr v2: warning fix (Alex) v3: squash in fix for thermal (Tom) Reviewed-by:
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- 19 Sep, 2017 1 commit
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Rex Zhu authored
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