1. 30 Dec, 2010 1 commit
    • Changhwan Youn's avatar
      ARM: S5PV310: Set bit 22 in the PL310 (cache controller) AuxCtlr register · a50eb1c7
      Changhwan Youn authored
      This patch is applied according to the commit 1a8e41cd
      (ARM: 6395/1: VExpress: Set bit 22 in the PL310 (cache controller) AuxCtlr register).
      
      Actually, S5PV310 has same cache controller(PL310).
      
      Following is from Catalin Marinas' commit.
      
      Clearing bit 22 in the PL310 Auxiliary Control register (shared
      attribute override enable) has the side effect of transforming Normal
      Shared Non-cacheable reads into Cacheable no-allocate reads.
      
      Coherent DMA buffers in Linux always have a Cacheable alias via the
      kernel linear mapping and the processor can speculatively load cache
      lines into the PL310 controller. With bit 22 cleared, Non-cacheable
      reads would unexpectedly hit such cache lines leading to buffer
      corruption.
      Signed-off-by: default avatarChanghwan Youn <chaos.youn@samsung.com>
      Cc: <stable@kernel.org>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Russell King <rmk+kernel@arm.linux.org.uk>
      Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
      a50eb1c7
  2. 29 Dec, 2010 1 commit
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