- 18 Mar, 2021 12 commits
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Álvaro Fernández Rojas authored
Add device tree support to b53_mmap.c while keeping platform devices support. Signed-off-by:
Álvaro Fernández Rojas <noltari@gmail.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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David S. Miller authored
Mohammad Athari Bin Ismail says: ==================== net: stmmac: EST interrupts and ethtool This patchset adds support for handling EST interrupts and reporting EST errors. Additionally, the errors are added into ethtool statistic. ==================== Signed-off-by: -
Ong Boon Leong authored
Below EST errors are added into ethtool statistic: 1) Constant Gate Control Error (CGCE): The counter "mtl_est_cgce" increases everytime CGCE interrupt is triggered. 2) Head-of-Line Blocking due to Scheduling (HLBS): The counter "mtl_est_hlbs" increases everytime HLBS interrupt is triggered. 3) Head-of-Line Blocking due to Frame Size (HLBF): The counter "mtl_est_hlbf" increases everytime HLBF interrupt is triggered. 4) Base Time Register error (BTRE): The counter "mtl_est_btre" increases everytime BTRE interrupt is triggered but BTRL not reaches maximum value of 15. 5) Base Time Register Error Loop Count (BTRL) reaches maximum value: The counter "mtl_est_btrlm" increases everytime BTRE interrupt is triggered and BTRL value reaches maximum value of 15. Please refer to MTL_EST_STATUS register in DesignWare Cores Ethernet Quality-of-Service Databook for more detail explanation. Signed-off-by:
Ong Boon Leong <boon.leong.ong@intel.com> Signed-off-by:
Voon Weifeng <weifeng.voon@intel.com> Co-developed-by:
Mohammad Athari Bin Ismail <mohammad.athari.ismail@intel.com> Signed-off-by:
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Voon Weifeng authored
Enabled EST related interrupts as below: 1) Constant Gate Control Error (CGCE) 2) Head-of-Line Blocking due to Scheduling (HLBS) 3) Head-of-Line Blocking due to Frame Size (HLBF). 4) Base Time Register error (BTRE) 5) Switch to S/W owned list Complete (SWLC) For HLBS, the user will get the info of all the queues that shows this error. For HLBF, the user will get the info of all the queue with the latest frame size which causes the error. Frame size 0 indicates no error. The ISR handling takes place when EST feature is enabled by user. Signed-off-by:
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David S. Miller authored
Ong Boon Leong says: ==================== stmmac: add VLAN priority based RX steering The current tc flower implementation in stmmac supports both L3 and L4 filter offloading. This patch adds the support of VLAN priority based RX frame steering into different Rx Queues. The patches have been tested on both configuration test (include L3/L4) and traffic test (multi VLAN ping streams with RX Frame Steering) below:- > tc qdisc delete dev eth0 ingress > tc qdisc del dev eth0 parent root 2&> /dev/null > tc qdisc del dev eth0 parent ffff: 2&> /dev/null > tc qdisc add dev eth0 ingress > tc filter add dev eth0 parent ffff: protocol ip flower dst_ip 192.168.0.1 \ src_ip 192.168.1.1 ip_proto tcp dst_port 5201 src_port 6201 action drop > tc filter add dev eth0 parent ffff: protocol ip flower dst_ip 192.168.0.2 \ src_ip 192.168.1.2 ip_proto tcp dst_port 5202 src_port 6202 action drop > tc filter show dev eth0 ingress filter parent ffff: protocol ip pref 49151 flower chain 0 filter parent ffff: protocol ip pref 49151 flower chain 0 handle 0x1 eth_type ipv4 ip_proto tcp dst_ip 192.168.0.2 src_ip 192.168.1.2 dst_port 5202 src_port 6202 in_hw in_hw_count 1 action order 1: gact action drop random type none pass val 0 index 2 ref 1 bind 1 filter parent ffff: protocol ip pref 49152 flower chain 0 filter parent ffff: protocol ip pref 49152 flower chain 0 handle 0x1 eth_type ipv4 ip_proto tcp dst_ip 192.168.0.1 src_ip 192.168.1.1 dst_port 5201 src_port 6201 in_hw in_hw_count 1 action order 1: gact action drop random type none pass val 0 index 1 ref 1 bind 1 > tc qdisc delete dev eth0 ingress > tc qdisc del dev eth0 parent root 2&> /dev/null > tc qdisc del dev eth0 parent ffff: 2&> /dev/null > tc qdisc add dev eth0 ingress > tc qdisc add dev eth0 root mqprio num_tc 4 \ map 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 \ queues 1@0 1@1 1@2 1@3 hw 0 > tc filter add dev eth0 parent ffff: protocol 802.1Q flower vlan_prio 0 hw_tc 3 > tc filter add dev eth0 parent ffff: protocol 802.1Q flower vlan_prio 1 hw_tc 2 > tc filter add dev eth0 parent ffff: protocol 802.1Q flower vlan_prio 2 hw_tc 1 > tc filter add dev eth0 parent ffff: protocol 802.1Q flower vlan_prio 3 hw_tc 0 > tc filter show dev eth0 ingress filter parent ffff: protocol 802.1Q pref 49149 flower chain 0 filter parent ffff: protocol 802.1Q pref 49149 flower chain 0 handle 0x1 hw_tc 0 vlan_prio 3 in_hw in_hw_count 1 filter parent ffff: protocol 802.1Q pref 49150 flower chain 0 filter parent ffff: protocol 802.1Q pref 49150 flower chain 0 handle 0x1 hw_tc 1 vlan_prio 2 in_hw in_hw_count 1 filter parent ffff: protocol 802.1Q pref 49151 flower chain 0 filter parent ffff: protocol 802.1Q pref 49151 flower chain 0 handle 0x1 hw_tc 2 vlan_prio 1 in_hw in_hw_count 1 filter parent ffff: protocol 802.1Q pref 49152 flower chain 0 filter parent ffff: protocol 802.1Q pref 49152 flower chain 0 handle 0x1 hw_tc 3 vlan_prio 0 in_hw in_hw_count 1 > tc qdisc delete dev eth0 ingress > ip address flush dev eth0 > ip address add 169.254.1.11/24 dev eth0 > ip link delete dev eth0.vlan1 2> /dev/null > ip link add link eth0 name eth0.vlan1 type vlan id 1 > ip address flush dev eth0.vlan1 2> /dev/null > ip address add 169.254.11.11/24 dev eth0.vlan1 > ip link delete dev eth0.vlan2 2> /dev/null > ip link add link eth0 name eth0.vlan2 type vlan id 2 > ip address flush dev eth0.vlan2 2> /dev/null > ip address add 169.254.12.11/24 dev eth0.vlan2 > ip link delete dev eth0.vlan3 2> /dev/null > ip link add link eth0 name eth0.vlan3 type vlan id 3 > ip address flush dev eth0.vlan3 2> /dev/null > ip address add 169.254.13.11/24 dev eth0.vlan3 > ip link delete dev eth0.vlan4 2> /dev/null > ip link add link eth0 name eth0.vlan4 type vlan id 4 > ip address flush dev eth0.vlan4 2> /dev/null > ip address add 169.254.14.11/24 dev eth0.vlan4 > ip address flush dev eth0 > ip address add 169.254.1.22/24 dev eth0 > ip link delete dev eth0.vlan1 2> /dev/null > ip link add link eth0 name eth0.vlan1 type vlan id 1 > ip address flush dev eth0.vlan1 2> /dev/null > ip address add 169.254.11.22/24 dev eth0.vlan1 > ip link delete dev eth0.vlan2 2> /dev/null > ip link add link eth0 name eth0.vlan2 type vlan id 2 > ip address flush dev eth0.vlan2 2> /dev/null > ip address add 169.254.12.22/24 dev eth0.vlan2 > ip link delete dev eth0.vlan3 2> /dev/null > ip link add link eth0 name eth0.vlan3 type vlan id 3 > ip address flush dev eth0.vlan3 2> /dev/null > ip address add 169.254.13.22/24 dev eth0.vlan3 > ip link delete dev eth0.vlan4 2> /dev/null > ip link add link eth0 name eth0.vlan4 type vlan id 4 > ip address flush dev eth0.vlan4 2> /dev/null > ip address add 169.254.14.22/24 dev eth0.vlan4 > mkdir -p /sys/fs/cgroup/net_prio/grp0 > echo eth0 0 > /sys/fs/cgroup/net_prio/grp0/net_prio.ifpriomap > echo eth0.vlan1 0 > /sys/fs/cgroup/net_prio/grp0/net_prio.ifpriomap > mkdir -p /sys/fs/cgroup/net_prio/grp1 > echo eth0 0 > /sys/fs/cgroup/net_prio/grp1/net_prio.ifpriomap > echo eth0.vlan2 1 > /sys/fs/cgroup/net_prio/grp1/net_prio.ifpriomap > mkdir -p /sys/fs/cgroup/net_prio/grp2 > echo eth0 0 > /sys/fs/cgroup/net_prio/grp2/net_prio.ifpriomap > echo eth0.vlan3 2 > /sys/fs/cgroup/net_prio/grp2/net_prio.ifpriomap > mkdir -p /sys/fs/cgroup/net_prio/grp3 > echo eth0 0 > /sys/fs/cgroup/net_prio/grp3/net_prio.ifpriomap > echo eth0.vlan4 3 > /sys/fs/cgroup/net_prio/grp3/net_prio.ifpriomap > tc qdisc del dev eth0 parent root 2&> /dev/null > tc qdisc del dev eth0 parent ffff: 2&> /dev/null > tc qdisc add dev eth0 ingress > tc qdisc add dev eth0 root mqprio num_tc 4 map 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 queues 1@0 1@1 1@2 1@3 hw 0 > tc filter add dev eth0 parent ffff: protocol 802.1Q flower vlan_prio 0 hw_tc 0 > tc filter add dev eth0 parent ffff: protocol 802.1Q flower vlan_prio 1 hw_tc 1 > tc filter add dev eth0 parent ffff: protocol 802.1Q flower vlan_prio 2 hw_tc 2 > tc filter add dev eth0 parent ffff: protocol 802.1Q flower vlan_prio 3 hw_tc 3 > ip link set eth0.vlan1 type vlan egress-qos-map 0:0 > ip link set eth0.vlan2 type vlan egress-qos-map 1:1 > ip link set eth0.vlan3 type vlan egress-qos-map 2:2 > ip link set eth0.vlan4 type vlan egress-qos-map 3:3 > tc filter show dev eth0 ingress filter parent ffff: protocol 802.1Q pref 49149 flower chain 0 filter parent ffff: protocol 802.1Q pref 49149 flower chain 0 handle 0x1 hw_tc 3 vlan_prio 3 in_hw in_hw_count 1 filter parent ffff: protocol 802.1Q pref 49150 flower chain 0 filter parent ffff: protocol 802.1Q pref 49150 flower chain 0 handle 0x1 hw_tc 2 vlan_prio 2 in_hw in_hw_count 1 filter parent ffff: protocol 802.1Q pref 49151 flower chain 0 filter parent ffff: protocol 802.1Q pref 49151 flower chain 0 handle 0x1 hw_tc 1 vlan_prio 1 in_hw in_hw_count 1 filter parent ffff: protocol 802.1Q pref 49152 flower chain 0 filter parent ffff: protocol 802.1Q pref 49152 flower chain 0 handle 0x1 hw_tc 0 vlan_prio 0 in_hw in_hw_count 1 > echo 1 > /proc/irq/131/smp_affinity > echo 1 > /proc/irq/132/smp_affinity > echo 4 > /proc/irq/133/smp_affinity > echo 4 > /proc/irq/134/smp_affinity > echo 4 > /proc/irq/135/smp_affinity > echo 4 > /proc/irq/136/smp_affinity > echo 2 > /proc/irq/137/smp_affinity > echo 2 > /proc/irq/138/smp_affinity > ping -i 0.001 169.254.11.22 2&> /dev/null & > PID1="$!" > echo $PID1 > /sys/fs/cgroup/net_prio/grp0/cgroup.procs > ping -i 0.001 169.254.12.22 2&> /dev/null & > PID2="$!" > echo $PID2 > /sys/fs/cgroup/net_prio/grp1/cgroup.procs > ping -i 0.001 169.254.13.22 2&> /dev/null & > PID3="$!" > echo $PID3 > /sys/fs/cgroup/net_prio/grp2/cgroup.procs > ping -i 0.001 169.254.14.22 2&> /dev/null & > PID4="$!" > echo $PID4 > /sys/fs/cgroup/net_prio/grp3/cgroup.procs > ping -i 0.001 169.254.11.11 2&> /dev/null & > PID1="$!" > echo $PID1 > /sys/fs/cgroup/net_prio/grp0/cgroup.procs > ping -i 0.001 169.254.12.11 2&> /dev/null & > PID2="$!" > echo $PID2 > /sys/fs/cgroup/net_prio/grp1/cgroup.procs > ping -i 0.001 169.254.13.11 2&> /dev/null & > PID3="$!" > echo $PID3 > /sys/fs/cgroup/net_prio/grp2/cgroup.procs > ping -i 0.001 169.254.14.11 2&> /dev/null & > PID4="$!" > echo $PID4 > /sys/fs/cgroup/net_prio/grp3/cgroup.procs > watch -n 0.5 -d "cat /proc/interrupts | grep eth0" 131: 251918 41 0 0 IR-PCI-MSI 477184-edge eth0:rx-0 132: 18969 1 0 0 IR-PCI-MSI 477185-edge eth0:tx-0 133: 0 0 295872 0 IR-PCI-MSI 477186-edge eth0:rx-1 134: 0 0 16136 0 IR-PCI-MSI 477187-edge eth0:tx-1 135: 0 0 288042 0 IR-PCI-MSI 477188-edge eth0:rx-2 136: 0 0 16135 0 IR-PCI-MSI 477189-edge eth0:tx-2 137: 0 211177 0 0 IR-PCI-MSI 477190-edge eth0:rx-3 138: 2 16144 0 0 IR-PCI-MSI 477191-edge eth0:tx-3 139: 0 0 0 0 IR-PCI-MSI 477192-edge eth0:rx-4 140: 0 0 0 0 IR-PCI-MSI 477193-edge eth0:tx-4 141: 0 0 0 0 IR-PCI-MSI 477194-edge eth0:rx-5 142: 0 0 0 0 IR-PCI-MSI 477195-edge eth0:tx-5 143: 0 0 0 0 IR-PCI-MSI 477196-edge eth0:rx-6 144: 0 0 0 0 IR-PCI-MSI 477197-edge eth0:tx-6 145: 0 0 0 0 IR-PCI-MSI 477198-edge eth0:rx-7 146: 0 0 0 0 IR-PCI-MSI 477199-edge eth0:tx-7 157: 0 0 0 0 IR-PCI-MSI 477210-edge eth0:safety-ue ==================== Signed-off-by: -
Ong Boon Leong authored
We extend tc flower to support configuration of VLAN priority-based RX frame steering hardware offloading. To map VLAN <PCP> to Traffic Class <TC>: $ tc filter add dev <IFNAME> parent ffff: protocol 802.1Q flower \ vlan_prio <PCP> hw_tc <TC> Note: <TC> < N whereby "tc qdisc ... num_tc N ..." To delete all tc flower configurations: $ tc qdisc delete dev <IFNAME> ingress Signed-off-by: -
Ong Boon Leong authored
The current tc_add_flow() and tc_del_flow() use hardware L3 & L4 filters as offloading. The number of L3/L4 filters is read from L3L4FNUM field from MAC_HW_Feature1 register and is used to alloc priv->tc_entries[]. For RX frame steering based on VLAN priority offloading, we use MAC_RXQ_CTRL2 & MAC_RXQ_CTRL3 registers and all VLAN priority level can be configured independent from L3 & L4 filters. Signed-off-by:
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David S. Miller authored
Naveen Mamindlapalli says: ==================== Add tc hardware offloads This patch series adds support for tc hardware offloads. Patch #1 adds support for offloading flows that matches IP tos and IP protocol which will be used by tc hw offload support. Also added ethtool n-tuple filter to code to offload the flows matching the above fields. Patch #2 adds tc flower hardware offload support on ingress traffic. Patch #3 adds TC flower offload stats. Patch #4 adds tc TC_MATCHALL egress ratelimiting offload. * tc flower hardware offload in PF driver The driver parses the flow match fields and actions received from the tc subsystem and adds/delete MCAM rules for the same. Each flow contains set of match and action fields. If the action or fields are not supported, the rule cannot be offloaded to hardware. The tc uses same set of MCAM rules allocated for ethtool n-tuple filters. So, at a time only one entity can offload the flows to hardware, they're made mutually exclusive in the driver. Following match and actions are supported. Match: Eth dst_mac, EtherType, 802.1Q {vlan_id,vlan_prio}, vlan EtherType, IP proto {tcp,udp,sctp,icmp,icmp6}, IPv4 tos, IPv4{dst_ip,src_ip}, L4 proto {dst_port|src_port number}. Actions: drop, accept, vlan pop, redirect to another port on the device. The Hardware stats are also supported. Currently only packet counter stats are updated. * tc egress rate limiting support Added TC-MATCHALL classifier offload with police action applied for all egress traffic on the specified interface. ==================== Signed-off-by: -
Sunil Goutham authored
Add TC_MATCHALL egress ratelimiting offload support with POLICE action for entire traffic going out of the interface. Eg: To ratelimit egress traffic to 100Mbps $ ethtool -K eth0 hw-tc-offload on $ tc qdisc add dev eth0 clsact $ tc filter add dev eth0 egress matchall skip_sw \ action police rate 100Mbit burst 16Kbit HW supports a max burst size of ~128KB. Only one ratelimiting filter can be installed at a time. Signed-off-by:Sunil Goutham <sgoutham@marvell.com> Signed-off-by:
Naveen Mamindlapalli <naveenm@marvell.com> Signed-off-by:
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Naveen Mamindlapalli authored
Add support to get the stats for tc flower flows that are offloaded to hardware. To support this feature, added a new AF mbox handler which returns the MCAM entry stats for a flow that has hardware stat counter enabled. Signed-off-by:
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Naveen Mamindlapalli authored
This patch adds support for tc flower hardware offload on ingress traffic. Since the tc-flower filter rules use the same set of MCAM rules as the n-tuple filters, the n-tuple filters and tc flower rules are mutually exclusive. When one of the feature is enabled using ethtool, the other feature is disabled in the driver. By default the driver enables n-tuple filters during initialization. The following flow keys are supported. -> Ethernet: dst_mac -> L2 proto: all protocols -> VLAN (802.1q): vlan_id/vlan_prio -> IPv4: dst_ip/src_ip/ip_proto{tcp|udp|sctp|icmp}/ip_tos -> IPv6: ip_proto{icmpv6} -> L4(tcp/udp/sctp): dst_port/src_port The following flow actions are supported. -> drop -> accept -> redirect -> vlan pop The flow action supports multiple actions when vlan pop is specified as the first action. The redirect action supports redirecting to the PF/VF of same PCI device. Redirecting to other PCI NIX devices is not supported. Example #1: Add a tc filter rule to drop UDP traffic with dest port 80 # ethtool -K eth0 hw-tc-offload on # tc qdisc add dev eth0 ingress # tc filter add dev eth0 protocol ip parent ffff: flower ip_proto \ udp dst_port 80 action drop Example #2: Add a tc filter rule to redirect ingress traffic on eth0 with vlan id 3 to eth6 (ex: eth0 vf0) after stripping the vlan hdr. # ethtool -K eth0 hw-tc-offload on # tc qdisc add dev eth0 ingress # tc filter add dev eth0 parent ffff: protocol 802.1Q flower \ vlan_id 3 vlan_ethtype ipv4 action vlan pop action mirred \ ingress redirect dev eth6 Example #3: List the ingress filter rules # tc -s filter show dev eth4 ingress Example #4: Delete tc flower filter rule with handle 0x1 # tc filter del dev eth0 ingress protocol ip pref 49152 \ handle 1 flower Signed-off-by: -
Naveen Mamindlapalli authored
Add support for programming the HW MCAM match key with IP tos, IP(v6) proto icmp/icmpv6, allowing flow offload rules to be installed using those fields. The NPC HW extracts layer type, which will be used as a matching criteria for different IP protocols. The ethtool n-tuple filter logic has been updated to parse the IP tos and l4proto for HW offloading. l4proto tcp/udp/sctp/ah/esp/icmp are supported. See example usage below. Ex: Redirect l4proto icmp to vf 0 queue 0 ethtool -U eth0 flow-type ip4 l4proto 1 action vf 0 queue 0 Ex: Redirect flow with ip tos 8 to vf 0 queue 0 ethtool -U eth0 flow-type ip4 tos 8 vf 0 queue 0 Signed-off-by:
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- 17 Mar, 2021 28 commits
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Michael Tretter authored
On some platforms, e.g., the ZynqMP, devm_clk_get can return -EPROBE_DEFER if the clock controller, which is implemented in firmware, has not been probed yet. As clk_init is only called during probe, use dev_err_probe to simplify the error message and hide it for -EPROBE_DEFER. Signed-off-by:
Michael Tretter <m.tretter@pengutronix.de> Acked-by:
Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by:
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David S. Miller authored
Marek Behún says: ==================== Add support for mv88e6393x family of Marvell after 2 months I finally had time to send v17 of Amethyst patches. This series is tested on Marvell CN9130-CRB. Changes since v16: - dropped patches adding 5gbase-r, since they are already merged - rebased onto net-next/master - driver API renamed set_egress_flood() method into 2 methods for ucast/mcast floods, so this is fixed Changes from v15: - put 10000baseKR_Full back into phylink_validate method for Amethyst, it seems I misunderstood the meaning behind things and removed it from v15 - removed erratum 3.7, since the procedure is done anyway in mv88e6390_serdes_pcs_config - renumbered errata 3.6 and 3.8 to 4.6 and 4.8, according to newer version of the errata document - refactored errata code a little and removed duplicate macro definitions (for example MV88E6390_SGMII_CONTROL is already called MV88E6390_SGMII_BMCR) Changes from v14: - added my Signed-off-by tags to Pavana's patches, since I am sending them (as suggested by Andrew) - added documentation to second patch adding 5gbase-r mode (as requested by Russell) - added Reviewed-by tags - applied Vladimir's suggestions: - reduced indentation level in mv88e6xxx_set_egress_port and mv88e6393x_serdes_port_config - removed 10000baseKR_Full from mv88e6393x_phylink_validate - removed PHY_INTERFACE_MODE_10GKR from mv88e6xxx_port_set_cmode Changes from v13: - added patch that wraps .set_egress_port into mv88e6xxx_set_egress_port, so that we do not have to set chip->*gress_dest_port members in every implementation of this method - for the patch that adds Amethyst support: - added more information into commit message - added these methods for mv88e6393x_ops: .port_sync_link .port_setup_message_port .port_max_speed_mode (new implementation needed) .atu_get_hash .atu_set_hash .serdes_pcs_config .serdes_pcs_an_restart .serdes_pcs_link_up - this device can set upstream port per port, so implement .port_set_upstream_port instead of .set_cpu_port - removed USXGMII cmode (not yet supported, working on it) - added debug messages into mv88e6393x_port_set_speed_duplex - added Amethyst errata 4.5 (EEE should be disabled on SERDES ports) - fixed 5gbase-r serdes configuration and interrupt handling - refactored mv88e6393x_serdes_setup_errata - refactored mv88e6393x_port_policy_write - added patch implementing .port_set_policy for Amethyst ==================== Signed-off-by: -
Marek Behún authored
The 16-bit Port Policy CTL register from older chips is on 6393x changed to Port Policy MGMT CTL, which can access more data, but indirectly and via 8-bit registers. The original 16-bit value is divided into first two 8-bit register in the Port Policy MGMT CTL. We can therefore use the previous code to compute the mask and shift, and then - if 0 <= shift < 8, we access register 0 in Port Policy MGMT CTL - if 8 <= shift < 16, we access register 1 in Port Policy MGMT CTL There are in fact other possible policy settings for Amethyst which could be added here, but this can be done in the future. Signed-off-by:
Marek Behún <kabel@kernel.org> Reviewed-by:
Pavana Sharma <pavana.sharma@digi.com> Reviewed-by:
Vladimir Oltean <olteanv@gmail.com> Signed-off-by:
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Pavana Sharma authored
The Marvell 88E6393X device is a single-chip integration of a 11-port Ethernet switch with eight integrated Gigabit Ethernet (GbE) transceivers and three 10-Gigabit interfaces. This patch adds functionalities specific to mv88e6393x family (88E6393X, 88E6193X and 88E6191X). The main differences between previous devices and this one are: - port 0 can be a SERDES port - all SERDESes are one-lane, eg. no XAUI nor RXAUI - on the other hand the SERDESes can do USXGMII, 10GBASER and 5GBASER (on 6191X only one SERDES is capable of more than 1g; USXGMII is not yet supported with this change) - Port Policy CTL register is changed to Port Policy MGMT CTL register, via which several more registers can be accessed indirectly - egress monitor port is configured differently - ingress monitor/CPU/mirror ports are configured differently and can be configured per port (ie. each port can have different ingress monitor port, for example) - port speed AltBit works differently than previously - PHY registers can be also accessed via MDIO address 0x18 and 0x19 (on previous devices they could be accessed only via Global 2 offsets 0x18 and 0x19, which means two indirections; this feature is not yet leveraged with thiis commit) Co-developed-by:
Ashkan Boldaji <ashkan.boldaji@digi.com> Signed-off-by:
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Marek Behún authored
There are two implementations of the .set_egress_port method, and both of them, if successful, set chip->*gress_dest_port variable. To avoid code repetition, wrap this method into mv88e6xxx_set_egress_port. Signed-off-by:
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Pavana Sharma authored
Returning 0 is no more an error case with MV88E6393 family which has serdes lane numbers 0, 9 or 10. So with this change .serdes_get_lane will return lane number or -errno (-ENODEV or -EOPNOTSUPP). Signed-off-by:
Andrew Lunn <andrew@lunn.ch> Reviewed-by:
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dingsenjie authored
remove unneeded variable: "ret". Signed-off-by:
dingsenjie <dingsenjie@yulong.com> Signed-off-by:
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dingsenjie authored
remove unneeded variable: "ret". Signed-off-by:
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Ong Boon Leong authored
Extending the driver to support per-queue RX and TX coalesce settings in order to support below commands: To show per-queue coalesce setting:- $ ethtool --per-queue <DEVNAME> queue_mask <MASK> --show-coalesce To set per-queue coalesce setting:- $ ethtool --per-queue <DEVNAME> queue_mask <MASK> --coalesce \ [rx-usecs N] [rx-frames M] [tx-usecs P] [tx-frames Q] Signed-off-by:Jakub Kicinski <kuba@kernel.org> Signed-off-by:
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David S. Miller authored
Vladimir Oltean says: ==================== DSA/switchdev documentation fixups These are some small fixups after the recently merged documentation update. ==================== Signed-off-by: -
Vladimir Oltean authored
Since commit 9d5ef190 ("net: dsa: automatically bring up DSA master when opening user port"), DSA manages the administrative status of the host port automatically. Update the configuration steps to reflect this. Signed-off-by:
Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by:
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Vladimir Oltean authored
"make htmldocs" complains: configuration.rst:165: WARNING: duplicate label networking/dsa/configuration:single port, other instance in (...) configuration.rst:212: WARNING: duplicate label networking/dsa/configuration:bridge, other instance in (...) configuration.rst:252: WARNING: duplicate label networking/dsa/configuration:gateway, other instance in (...) And for good reason, because the "single port", "bridge" and "gateway" use cases are replicated twice, once for normal taggers and twice for DSA_TAG_PROTO_NONE. So when trying to reference these sections via a hyperlink such as: https://www.kernel.org/doc/html/latest/networking/dsa/configuration.html#single-port it will always reference the first occurrence, and never the second one. This change makes the "single port", "bridge" and "gateway" configuration examples consistent with the formatting used in the "Configuration showcases" subsection. Signed-off-by:
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Vladimir Oltean authored
"make htmldocs" produces these warnings: Documentation/networking/dsa/dsa.rst:468: WARNING: Unexpected indentation. Documentation/networking/dsa/dsa.rst:477: WARNING: Block quote ends without a blank line; unexpected unindent. Fixes: 8411abbc ("Documentation: networking: dsa: mention integration with devlink") Reported-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
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Vladimir Oltean authored
Even though this is clear from the context, it is nice to actually be grammatically correct. Fixes: 0f22ad45 ("Documentation: networking: switchdev: clarify device driver behavior") Reported-by:
Ido Schimmel <idosch@nvidia.com> Signed-off-by:
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Vladimir Oltean authored
It looks like "make htmldocs" produces this warning: Documentation/networking/switchdev.rst:482: WARNING: Unexpected indentation. Fixes: 0f22ad45 ("Documentation: networking: switchdev: clarify device driver behavior") Reported-by:
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David S. Miller authored
Naveen Mamindlapalli says: ==================== refactor code related to npc install flow This patchset refactors and cleans up the code associated with the npc install flow API, specifically to eliminate different code paths while installing MCAM rules by AF and PF. This makes the code easier to understand and maintain. Also added support for multi channel NIX promisc entry. ==================== Signed-off-by: -
Naveen Mamindlapalli authored
The mbox handler npc_install_flow returns ENOTSUPP for unsupported flow keys. This patch modifies the return value to AF driver defined error code for debugging purpose. Signed-off-by:
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Subbaraya Sundeep authored
A mcam rule described by mcam_rule struct has all the info such as the hardware MCAM entry number, match criteria and corresponding action etc. All mcam rules are stored in a linked list mcam->rules. When adding/updating a rule to the mcam->rules it is checked if a rule already exists for the mcam entry. If the rule already exists, the same rule is updated instead of creating new rule. This way only one mcam_rule exists for the only one default unicast entry installed by AF. But a PF/VF can get different NIXLF (or default unicast entry number) after a attach-detach-attach sequence. When that happens mcam_rules list end up with two default unicast rules. Fix the problem by deleting the default unicast rule list node always when disabling mcam rules. Signed-off-by:
Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by:
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Naveen Mamindlapalli authored
Use npc_install_flow mailbox API for installing the default promisc and broadcast match entries. Earlier these entries were installed using low level npc_config_mcam_entry API, which does not store these rules and is not available when the rules are dumped using debugfs. Added chan_mask field to npc_install_flow_req to calculate channel mask when channel count is greater than 1 and configure the channel mask in entry kw_mask. Signed-off-by:
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Nalla, Pradeep authored
This patch adds support for multi channel NIX promisc entry. Packets sent on all those channels by the host should be received by the interface to which those channels belong. Channel count, if greater than 1, should be power of 2 as only one promisc entry is available for the interface. Key mask is modified such that incoming packets from channel base to channel count are directed to the same pci function. Signed-off-by:
Nalla, Pradeep <pnalla@marvell.com> Signed-off-by:
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Naveen Mamindlapalli authored
This patch refactors npc_install_flow function to install AF installed default MCAM entries similar to other MCAM entries installed by PF/VF. As a result the code would be more readable and easy to maintain. Modified npc_verify_entry and npc_verify_channel to properly check MCAM rules installed by AF. Signed-off-by:
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David S. Miller authored
mlxsw: Allow 802.1d and .1ad VxLAN bridges to coexist on Spectrum>=2 Ido Schimmel says: ==================== This patchset allows user space to simultaneously configure both 802.1d and 802.1ad VxLAN bridges on Spectrum-2 and later ASICs. 802.1ad VxLAN bridges are still forbidden on Spectrum-1. The reason for the current limitation is that up until now the EtherType that was pushed to decapsulated VxLAN packets was a property of the tunnel port, of which there is only one. This meant that a 802.1ad VxLAN bridge could not be configured if the tunnel port was already configured to push a 802.1q tag. This patchset improves the situation by making two changes. First, decapsulated packets are marked as having their EtherType decided by the egress port. Second, local ports member in the bridge (e.g., swp1) are configured to set the correct egress EtherType. Patchset overview: Patch #1 adds a register required for the first change Patches #2-#3 add the register required for the second change and a corresponding API Patch #4 prepares the driver for the split in behavior between Spectrum-1 and later ASICs Patch #5 performs the two above mentioned changes to allow the driver to support simultaneous 802.1ad and 802.1d VxLAN bridges on Spectrum-2 and later ASICs Patch #6 adds a selftest Patch #7 removes a selftest that verified the limitation that was lifted by this patchset ==================== Signed-off-by: -
Amit Cohen authored
q_in_vni_veto.sh is not needed anymore because VxLAN with an 802.1ad bridge and VxLAN with an 802.1d bridge can coexist. Remove the test. Signed-off-by:
Amit Cohen <amcohen@nvidia.com> Signed-off-by:
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Amit Cohen authored
Configure VxLAN with an 802.1ad bridge and VxLAN with an 802.1d bridge at the same time in same switch, verify that traffic passed as expected. Signed-off-by:
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Amit Cohen authored
Currently only one EtherType can be configured for pushing in tunnels because EtherType is configured using SPVID.et_vlan for tunnel port. This behavior is forbidden by comparing mlxsw_sp_nve_config struct for each new tunnel, the struct contains 'ethertype' field which means that only one EtherType is legal at any given time. Remove 'ethertype' field to allow creating VxLAN devices with different bridges. To allow using several types of VxLAN bridges at the same time, the EtherType should be determined at the egress port. This behavior is achieved by setting SPVID to decide which EtherType to push at egress and for each local_port which is member in 802.1ad bridge, set SPEVET.et_vlan to ether_type1 (i.e., 0x88A8). Use switchdev_ops->init() to set different mlxsw_sp_bridge_ops for different ASICs in order to be able to split the behavior when port joins / leaves an 802.1ad bridge in different ASICs. Signed-off-by:
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Amit Cohen authored
A subsequent patch will need to implement different set of operations when a port joins / leaves an 802.1ad bridge, based on the ASIC type. Prepare for this change by allowing to initialize the bridge module based on the ASIC type via 'struct mlxsw_sp_switchdev_ops'. Signed-off-by:
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Amit Cohen authored
A subsequent patch will cause decapsulated packets to have their EtherType determined by the egress port. Add mlxsw_sp_port_egress_ethtype_set() which will be called when a port joins an 802.1ad bridge, so that it will set an 802.1ad EtherType on decapsulated packets transmitted through it, instead of the default 802.1q EtherType. Signed-off-by:
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Amit Cohen authored
SPEVET configures which EtherType to push at egress for packets incoming through a local port for which 'SPVID.egr_et_set' is set. The next patches will use SPEVET to configure EtherType 0x88A8 and 0x8100 for local ports member in 802.1ad and 802.1q bridges, respectively. This allows using dual VxLAN bridges (802.1d and 802.1ad at the same time). Signed-off-by:
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