1. 18 May, 2004 1 commit
  2. 17 May, 2004 3 commits
  3. 16 May, 2004 12 commits
  4. 15 May, 2004 24 commits
    • Jeff Garzik's avatar
      Merge redhat.com:/spare/repo/b44-2.6.5 · 170747d7
      Jeff Garzik authored
      into redhat.com:/spare/repo/net-drivers-2.6
      170747d7
    • Pekka Pietikäinen's avatar
      [netdrvr b44] better reset behavior · 694919c6
      Pekka Pietikäinen authored
      This patch makes the b44-after-bcm4400 scenario work for
      me. What was happening is that the broadcom driver sets a "power off MAC"
      bit, and we didn't remove that when initializing the chip.
      Also added some (a bit ugly, I know  ) logic to clear up the address
      filter stuff, which is what recent broadcom drivers do...
      694919c6
    • Jeff Garzik's avatar
      [libata] handle non-data ATAPI commands via interrupt · 80e00375
      Jeff Garzik authored
      It's easier to do it this way, than polling, at the moment.
      
      Also, fix a test in ata_scsi_translate that was incorrectly
      erroring-out non-data commands.
      80e00375
    • Jeff Garzik's avatar
      [libata] minor stuff · 96b2b4d7
      Jeff Garzik authored
      * now that ATAPI is close to working, making ATAPI DMA interrupts
        in ata_host_intr
      * remove unnecessary space character in printk() output (oh, the horror)
      96b2b4d7
    • Richard Henderson's avatar
      [PATCH] alpha: fix GP-load symbol linkage · 054852c4
      Richard Henderson authored
      From: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
      
      This skips the GP-loading function prologue (two instructions: 8 bytes)
      on BRSGP linkage correctly, fixing an oops on alpha while loading the
      aic7xxx driver.
      054852c4
    • Linus Torvalds's avatar
      We need to use "memset_io()" when accessing PCI · ed40244e
      Linus Torvalds authored
      mapped memory.
      
      A regular "memset()" may be using cache control
      instructions etc, which is not appropriate for
      memory-mapped IO.
      
      This also fixes a warning.
      ed40244e
    • Linus Torvalds's avatar
      Merge bk://bk.arm.linux.org.uk/linux-2.6-rmk · 18857d8e
      Linus Torvalds authored
      into ppc970.osdl.org:/home/torvalds/v2.6/linux
      18857d8e
    • Robin Farine's avatar
      [ARM PATCH] 1879/1: fix a few xscale "drain write & fill buffer" instructions · cd594a3b
      Robin Farine authored
      Patch from Robin Farine
      
      Fix the xscale cache handling routines that were invalidating a D 
      cache line instead of draining the write & fill buffer as intended.
      cd594a3b
    • Catalin Marinas's avatar
      [ARM PATCH] 1883/1: Bit 4 in pmd should be 0 for the ARMv6 architecture · 6ef8f0dc
      Catalin Marinas authored
      Patch from Catalin Marinas
      
      Unlike the v5 architecture, the ARM1136 requires that BIT4 is 0 in
      the first level page descriptor (ARM1136 TRM, page 6-39). It works
      at the moment but it might break future v6 cores.
      6ef8f0dc
    • Catalin Marinas's avatar
      [ARM PATCH] 1882/1: Fixes in the v6_dma_(invalidate|flush)_range functions · dc1b0aa3
      Catalin Marinas authored
      Patch from Catalin Marinas
      
      The v6_dma_invalidate_range - the "mcr" instruction for draining
      
      the write buffer requires r0 == 0. A "cmp" instruction for
      
      testing the end address is missing in the v6_dma_flush_range
      
      function.
      dc1b0aa3
    • Catalin Marinas's avatar
      [ARM PATCH] 1881/1: Illegal strex instruction generated by gcc · 2b01a2d3
      Catalin Marinas authored
      Patch from Catalin Marinas
      
      The _raw_write_(try)lock functions in include/asm-arm/spinlock.h
      
      should use the early clobber modifier (&) for the "tmp" register.
      
      A newer compiler (gcc-3.4.0) generates an "strexeq %0, %1, [%2]"
      
      instruction where %0 is the same as %2, which is illegal.
      2b01a2d3
    • Catalin Marinas's avatar
      [ARM PATCH] 1880/1: cache_type is uninitialised in the blockops_check() function · 34dadab4
      Catalin Marinas authored
      Patch from Catalin Marinas
      
      In the blockops_check() function, cache_type is uninitialised
      
      because an "mcr" instruction is used instead of "mrc".
      34dadab4
    • Linus Torvalds's avatar
      Merge bk://bk.arm.linux.org.uk/linux-2.6-pcmcia · 73b5d164
      Linus Torvalds authored
      into ppc970.osdl.org:/home/torvalds/v2.6/linux
      73b5d164
    • Linus Torvalds's avatar
      Merge bk://bk.arm.linux.org.uk/linux-2.6-serial · ba1abdbf
      Linus Torvalds authored
      into ppc970.osdl.org:/home/torvalds/v2.6/linux
      ba1abdbf
    • Jan Kara's avatar
      [PATCH] Quota fix 2 · 64a3243b
      Jan Kara authored
      This fixes the problem with recursion into filesystem when inode of
      quota file needs a page + some other allocation problems.  I hope I got
      the GFP mask setting right..
      64a3243b
    • Linus Torvalds's avatar
      Merge bk://gkernel.bkbits.net/libata-2.6 · 48aa12e1
      Linus Torvalds authored
      into ppc970.osdl.org:/home/torvalds/v2.6/linux
      48aa12e1
    • Jeff Garzik's avatar
      [libata] internal cleanups · 50112a63
      Jeff Garzik authored
      Remove unused 'done_late' arg to ata_qc_complete(), which was never
      useful in 2.4, and never used at all in 2.6.
      
      This allows us to eliminate the same arg from ata_dma_complete(),
      and also make it more correct by passing the command rather than
      the ATA port structure as arg0.
      50112a63
    • Jeff Garzik's avatar
      Merge redhat.com:/spare/repo/sata-hacks/atapi-hacks-2.6 · 1ad2c4d1
      Jeff Garzik authored
      into redhat.com:/spare/repo/libata-2.6
      1ad2c4d1
    • Linus Torvalds's avatar
      Fix gidsetsize == 0 for real this time. · 78479816
      Linus Torvalds authored
      We need to always allocate at least one indirect block
      pointer, since we always fill out blocks[0] even if
      we don't have any groups.
      78479816
    • Bartlomiej Zolnierkiewicz's avatar
      [PATCH] remove bogus drivers/ide/pci/cmd640.h · 584286cc
      Bartlomiej Zolnierkiewicz authored
      Trivia.
      
      CMD640 driver doesn't use generic IDE PCI code (it doesn't even include
      this header).
      584286cc
    • Bartlomiej Zolnierkiewicz's avatar
      [PATCH] ide-disk.c: more write cache fixes · 7e33820d
      Bartlomiej Zolnierkiewicz authored
      - many Maxtor disks incorrectly claim CACHE FLUSH EXT command support,
        fix it by checking both CACHE FLUSH EXT command and LBA48 support
        (thanks to Eric D. Mudama for help in fixing this)
      
      - write_cache() was called with 'drive->id->cfs_enable_2 & 0x3000' as 'int arg'
        argument which was always truncated to zero due to 'u8 drive->wcache = arg'
        assignment so write cache was indeed enabled but drive->wcache was zero
        (thanks to Rene Herman for help in debugging this)
      
      - flush cache in idedisk_start_power_step() only if ATA-6 CACHE FLUSH (EXT)
        bits are present in disk's identify data (prevents sending unknown commands)
      
      - set drive->wcache in idedisk_setup() not idedisk_attach() (no need to check
        id->command_set_2 - we check id->cfs_enable_2 instead in write_cache() call)
      
      - use ide_cacheflush_p() in idedisk_setup()
      
      - minor cleanups
      7e33820d
    • Andi Kleen's avatar
      [PATCH] Handle empty nodes in sysfs on x86-64 · ab9e69a3
      Andi Kleen authored
      This code is shared between i386 and x86-64, and x86-64 needs to check
      for empty nodes here.  Otherwise you can get oopses at boot in some
      circumstances. 
      
      This handles empty nodes != 0; empty node zero are still broken in other
      ways.
      ab9e69a3
    • Andi Kleen's avatar
      [PATCH] x86-64: fix /dev/mem caching behaviour · f1eda416
      Andi Kleen authored
      This changes the /dev/mem caching behaviour on x86-64 to be compatible
      with i386.
      
      By default everything is set cached.
      
      This actually makes WC MTRRs on AMD systems work, which would get
      overriden by the UC PAT bits that were set earlier.  This can make DVD
      decoding with hardware support a lot faster. 
      
      It also supports O_SYNC now, like i386, although that is not really
      safe, because it allows the user to create undefined cache attribute
      conflicts that can corrupt caches in some circumstances.  I kept it for
      now.  Better would to disallow it, until Terrence Ripperda's PAT
      framework is getting merged, that can avoid these problems. 
      
      Actually it would be probably a good idea to add a printk here to catch
      broken programs for i386 and x86-64, but that is for another patch.
      f1eda416
    • Andi Kleen's avatar
      [PATCH] x86-64 updates · fb75a3d4
      Andi Kleen authored
      Various accumulated x86-64 patches and bug fixes.
      
      It fixes one nasty bug that has been there since NX is used by 
      default in the kernel. With heavy AGP memory allocation it would
      set NX on parts of the kernel mapping in some corner cases, which gave
      endless crash loops. Thanks goes to some wizards in AMD debug labs
      for getting a trace out of this.
      
      Also various other fixes. This patches only changes x86-64 specific
      files, i have some changes outside too that I am sending separately.
      
       - Fix help test for CONFIG_NUMA
       - Don't enable SMT nice on CMP
       - Move HT and MWAIT checks up to generic code
       - Update defconfig
       - Remove duplicated includes (Arthur Othieno)
       - Set up GSI entry for ACPI SCI correctly (from i386)
       - Fix some comments
       - Fix threadinfo printing in oopses
       - Set task alignment to 16 bytes
       - Handle NX bit for code pages correctly in change_page_attr()
       - Use generic nops for non amd specific kernel
       - Add __KERNEL__ checks in unistd.h (David Lee)
      fb75a3d4