1. 19 Nov, 2018 9 commits
    • Eric Dumazet's avatar
      tun: use netdev_alloc_frag() in tun_napi_alloc_frags() · aa6daaca
      Eric Dumazet authored
      In order to cook skbs in the same way than Ethernet drivers,
      it is probably better to not use GFP_KERNEL, but rather
      use the GFP_ATOMIC and PFMEMALLOC mechanisms provided by
      netdev_alloc_frag().
      
      This would allow to use tun driver even in memory stress
      situations, especially if swap is used over this tun channel.
      
      Fixes: 90e33d45 ("tun: enable napi_gro_frags() for TUN/TAP driver")
      Signed-off-by: default avatarEric Dumazet <edumazet@google.com>
      Cc: Petar Penkov <peterpenkov96@gmail.com>
      Cc: Mahesh Bandewar <maheshb@google.com>
      Cc: Willem de Bruijn <willemb@google.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      aa6daaca
    • David S. Miller's avatar
      Merge branch 'IP101GR-devicetree-based-configuration-of-SEL_INTR32' · 05b0e1d6
      David S. Miller authored
      Martin Blumenstingl says:
      
      ====================
      IP101GR: devicetree based configuration of SEL_INTR32
      
      The IP101GR is a 32-pin QFN package variant of the IP101G/IP101GA
      Ethernet PHY. Due to it's limited amount of pins the RXER (receive
      error) and INTR32 (interrupt) functions share pin 21.
      
      The goal of this series is:
      - some small cleanups in patches 3, 4 and 5
      - allowing the kernel to detect IRQ floods on boards where the IP101GR
        is configured in RXER mode but the RXER line is configured on the
        host SoC as interrupt line (patch 6)
      - configuration of the SEL_INTR32 register so we can use the interrupt
        function on boards where the RXER/INTR32 pin (pin 21) is routed to
        one of the host SoC's interrupt inputs (patches 1, 2, 7)
      
      A use-case where this is needed is the Endless Mini (EC-100). I have
      tested my changes on that board. This also confirms that Heiner
      Kallweit's recent icplus.c PHY driver changes are working (at least on
      my setup).
      
      This series is based on net-next commit 7c460cf9 ("net: aquantia:
      fix spelling mistake "specfield" -> "specified"")
      
      Changes since v1 at [0]:
      - collected Andrew's Reviewed-by's (thank you!)
      - updated description of patch #2 to explain why two properties were
        added instead of adding an "this is a IP101GR" property
      - validate that there's no conflicting configuration in patch #7
      - rebased on top of latest net-next
      
      [0] https://patchwork.ozlabs.org/cover/999371/
      ====================
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      05b0e1d6
    • Martin Blumenstingl's avatar
      net: phy: icplus: allow configuring the interrupt function on IP101GR · f2f1a847
      Martin Blumenstingl authored
      The IP101GR is a 32-pin QFN package variant of the IP101G/IP101GA
      Ethernet PHY. Due to it's limited amount of pins the RXER (receive
      error) and INTR32 (interrupt) functions share pin 21.
      By default the PHY is configured to output the "receive error" status on
      pin 21. Depending on the board layout and requirements we may want to
      re-configure the PHY to output the interrupt signal there.
      
      The mode of pin 21 can be configured in the "Digital I/O Specific
      Control Register" (register 29), bit 2:
      - 0 = RXER function
      - 1 = INTR(32) function
      
      Depending on the devicetree configuration we will now:
      - change the mode to either ther RXER or INTR32 function
      - keep the SEL_INTR32 value set by the bootloader (default) if no
        configuration is provided (to ensure that we're not breaking existing
        boards)
      - error out if conflicting configuration is given (RXER and INTR32 mode
        are enabled at the same time)
      Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      f2f1a847
    • Martin Blumenstingl's avatar
      net: phy: icplus: implement .did_interrupt for IP101A/G · f7e290fb
      Martin Blumenstingl authored
      The IP101A_G_IRQ_CONF_STATUS register has bits to detect which
      interrupts have fired. Implement the .did_interrupt callback to let the
      PHY core know whether the interrupt was for this specific PHY.
      
      This is useful for debugging interrupt problems with 32-pin IP101GR PHYs
      where the interrupt line is shared with the RX_ERR (receive error
      status) signal. The default values are:
      - RX_ERR is enabled by default (LOW means that there is no receive
        error)
      - the PHY's interrupt line is configured "active low" by default
      
      Without any additional changes there is a flood of interrupts if the
      RX_ERR/INTR32 signal is configured in RX_ERR mode (which is the
      default). Having a did_interrupt ensures that the PHY core returns
      IRQ_NONE instead of endlessly triggering the PHY state machine.
      Additionally the kernel will report this after a while:
        irq 28: nobody cared (try booting with the "irqpoll" option)
      Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      f7e290fb
    • Martin Blumenstingl's avatar
      net: phy: icplus: rename IP101A_G_NO_IRQ to IP101A_G_IRQ_ALL_MASK · a872c388
      Martin Blumenstingl authored
      The datasheet uses the name "All Mask" for this bit. Change the name of
      our #define to be consistent with the datasheet. While here also replace
      the tab between the #define and IP101A_G_IRQ_ALL_MASK with a space.
      No functional changes.
      Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      a872c388
    • Martin Blumenstingl's avatar
      net: phy: icplus: use the BIT macro where possible · ee336140
      Martin Blumenstingl authored
      This makes the code consistent by using the BIT() macro instead of
      manual bit-shifting for some of the fields. No functional changes.
      Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      ee336140
    • Martin Blumenstingl's avatar
      net: phy: icplus: keep all ip101a_g functions together · 034289b2
      Martin Blumenstingl authored
      This simply moves ip101a_g_config_init right above
      ip101a_g_config_intr so all functions for the ICPlus IP101A/G PHYs are
      grouped together.
      No functional changes.
      Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      034289b2
    • Martin Blumenstingl's avatar
      dt-bindings: net: phy: add bindings for the IC Plus Corp. IP101A/G PHYs · fdc13a9e
      Martin Blumenstingl authored
      The IP101A and IP101G series both have various models. Depending on the
      board implementation we need a special property for the IP101GR (32-pin
      LQFP package) PHY:
      pin 21 ("RXER/INTR_32") outputs the "receive error" signal by default
      (LOW means "normal operation", HIGH means that there's either a decoding
      error of the received signal or that the PHY is receiving LPI). This pin
      can also be switched to INTR32 mode, where the interrupt signal is
      routed to this pin. The other PHYs don't need this special handling
      because they have more pins available so the interrupt function gets a
      dedicated pin.
      
      This adds two properties to either select the "receive error" or
      "interrupt" function of pin 21. Not specifying any function means that
      the default set by the bootloader is used. This is required because the
      IP101GR cannot be differentiated between other IP101 PHYs as the PHY
      identification registers on all of these is 0x02430c54.
      
      The IP101G (sold as die only, without package) may suffer from the same
      issue depending on how it's integrated into a multi chip package by
      another manufacturer. If only the RXER/INTR_32 pin is routed then the
      users of the die-only variant may also have to explicitly configure the
      mode of hte RXER/INTR_32 pin. This is the reason why no "is-ip101gr"
      property was added. I have no evidence though which would confirm this
      theory - so the binding itself is independent of that.
      Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
      Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      fdc13a9e
    • Martin Blumenstingl's avatar
      dt-bindings: vendor-prefix: add prefix for IC Plus Corp. · 8a49f9db
      Martin Blumenstingl authored
      IC Plus Corp. has various Ethernet related products such as Ethernet
      transceivers, Ethernet controllers, Ethernet switches, etc.
      Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      8a49f9db
  2. 18 Nov, 2018 29 commits
  3. 17 Nov, 2018 2 commits