- 16 Aug, 2024 27 commits
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Sunil Khatri authored
Add support of vcn ip dump in the devcoredump for vcn_v3_0. Signed-off-by:
Sunil Khatri <sunil.khatri@amd.com> Acked-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Sunil Khatri authored
Add pointer to the vcn ip dump in the vcn global structure to be accessible for all vcn version via global adev. Signed-off-by:
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Zhang Zekun authored
amdgpu_gart_table_vram_pin() and amdgpu_gart_table_vram_unpin() has been removed since commit 575e55ee ("drm/amdgpu: recover gart table at resume") remain the declarations untouched in the header files. Besides, amdgpu_dm_display_resume() has also beed removed since commit a80aa93d ("drm/amd/display: Unify dm resume sequence into a single call"). So, let's remove this unused declarations. Signed-off-by:
Zhang Zekun <zhangzekun11@huawei.com> Signed-off-by:
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Nikita Zhandarovich authored
Several cs track offsets (such as 'track->db_s_read_offset') either are initialized with or plainly take big enough values that, once shifted 8 bits left, may be hit with integer overflow if the resulting values end up going over u32 limit. Same goes for a few instances of 'surf.layer_size * mslice' multiplications that are added to 'offset' variable - they may potentially overflow as well and need to be validated properly. While some debug prints in this code section take possible overflow issues into account, simply casting to (unsigned long) may be erroneous in its own way, as depending on CPU architecture one is liable to get different results. Fix said problems by: - casting 'offset' to fixed u64 data type instead of ambiguous unsigned long. - casting one of the operands in vulnerable to integer overflow cases to u64. - adjust format specifiers in debug prints to properly represent 'offset' values. Found by Linux Verification Center (linuxtesting.org) with static analysis tool SVACE. Fixes: 285484e2 ("drm/radeon: add support for evergreen/ni tiling informations v11") Signed-off-by:
Nikita Zhandarovich <n.zhandarovich@fintech.ru> Signed-off-by:
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Yang Wang authored
Skip rlc firmware validation to ignore firmware header size mismatch issues. This restores the workaround added in commit 849e133c ("drm/amdgpu: Fix the null pointer when load rlc firmware") Fixes: 3af2c80a ("drm/amdgpu: refine gfx10 firmware loading") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3551Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
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Sunil Khatri authored
Remove ME0 registers from MI300 gfx_9_4_3 ipdump MI300 does not have gfx ME and hence those register are just empty one and could be dropped. Signed-off-by:
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Alex Deucher authored
Protect the MMIO access with safe mode. Acked-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Signed-off-by:
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Alex Deucher authored
Protect the MMIO access with safe mode. Acked-by:
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Alex Deucher authored
Rather than open coding it for the queue reset. Acked-by:
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Alex Deucher authored
Rather than open coding it for the queue reset. Acked-by:
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Alex Deucher authored
Add ring reset callback for gfx. Acked-by:
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Alex Deucher authored
It's not supported under SR-IOV at the moment. Acked-by:
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Jiadong Zhu authored
Using mmio to do queue reset. Enter safe mode before writing mmio registers. v2: set register instance offset according to xcc id. Acked-by:
Jiadong Zhu <Jiadong.Zhu@amd.com> Reviewed-by:
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Jiadong Zhu authored
Using mmio to do queue reset. Enter safe mode when writing registers. Acked-by:
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Jiadong Zhu authored
Add reset_hw_queue in kiq_pm4_funcs callbacks. Acked-by:
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Jiadong Zhu authored
There is a racing condition that cp firmware modifies MQD in reset sequence after driver updates it for remapping. We have to wait till CP_HQD_ACTIVE becoming false then remap the queue. v2: fix KIQ locking (Alex) v3: fix KIQ locking harder Acked-by:
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Jiadong Zhu authored
Kiq command unmap_queues only does the dequeueing action. We have to map the queue back with clean mqd. Acked-by:
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Alex Deucher authored
Add ring reset callback for compute. Acked-by:
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Jiadong Zhu authored
There is a racing condition that cp firmware modifies MQD in reset sequence after driver updates it for remapping. We have to wait till CP_HQD_ACTIVE becoming false then remap the queue. v2: fix KIQ locking (Alex) v3: fix KIQ locking harder Acked-by:
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Jiadong Zhu authored
Kiq command unmap_queues only does the dequeueing action. We have to map the queue back with clean mqd. Acked-by:
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Alex Deucher authored
Add ring reset callback for compute. Acked-by:
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Prike Liang authored
Update the reset counter for the amdgpu_cs_query_reset_state() Acked-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
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Alex Deucher authored
If a specific job is hung, try and reset just the ring associated with the job. v2: move to amdgpu_job.c v3: fix drm_sched_stop() handling when ring reset fails v4: drop unnecessary amdgpu_fence_driver_clear_job_fences() and drm_sched_increase_karma() v5: rework sched_stop handling Acked-by: -
Alex Deucher authored
Use this to reset just a single ring. Acked-by:
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Soham Dandapat authored
As we don't trigger preemption is sw ring muxer when mcbp is disabled,so return earlier in amdgpu_sw_ring_ib_end function if mcbp is disabled ,not required to call amdgpu_ring_mux_end_ib Signed-off-by:
Soham Dandapat <sdandapa@amd.com> Acked-by:
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Sunil Khatri authored
Add gfx9_4_3 print support of CP queue registers for all queues to be used by devcoredump. Signed-off-by:
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Sunil Khatri authored
Add gfx9 support of CP queue registers for all queues to be used by devcoredump. Signed-off-by:
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- 13 Aug, 2024 13 commits
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Srinivasan Shanmugam authored
The descriptor for `hwss_wait_for_all_blank_complete` was previously misaligned with the actual implementation. This commit refines the descriptor to reflect the implementation of `hwss_wait_for_all_blank_complete` Fixes the below with gcc W=1: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_hw_sequencer.c:991: warning: expecting prototype for hwss_wait_for_blank_complete(). Prototype was for hwss_wait_for_all_blank_complete() instead Cc: Tom Chung <chiahsuan.chung@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Cc: Roman Li <roman.li@amd.com> Cc: Alex Hung <alex.hung@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
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Sunil Khatri authored
Add support of gfx9_4_3 ipdump print so devcoredump could trigger it to dump the captured registers in devcoredump. Signed-off-by:
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Sunil Khatri authored
Add general registers of gfx9_4_3 in ipdump for devcoredump support. Signed-off-by:
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David (Ming Qiang) Wu authored
Because gpu_addr is updated in the calling routine (amdgpu_cs_patch_ibs()),it is removed in the callback. Use .patch_cs_in_place instead of .parse_cs for amdgpu_vce_ring_parse_cs_vm() as there is no need for keeping a temporary IB, therefore ib->sa_bo is NULL and amdgpu_ib_free() is removed. Reviewed-by:
David (Ming Qiang) Wu <David.Wu3@amd.com> Signed-off-by:
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David (Ming Qiang) Wu authored
Add JPEG IB command parser to ensure registers in the command are within the JPEG IP block. Reviewed-by:
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Jack Xiao authored
Use mes pipe to unmap kcq and kgq. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Acked-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Jack Xiao authored
Free memory for two pipes and unmap pipe0 via pipe1. Signed-off-by:
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Jack Xiao authored
Configure two pipes with different hardware resources. Signed-off-by:
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Jack Xiao authored
Adjust mes12 sw/hw initiailization for both pipe0 and pipe1 enablement. The two pipes are almost identical pipe. Pipe0 behaves like schq and pipe1 like kiq, pipe0 was mapped by pipe1. Signed-off-by:
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Jack Xiao authored
Add mes pipe switch to let caller choose pipe to submit packet. Signed-off-by:
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Victor Skvortsov authored
Register access from userspace should be blocked until reset is complete. Signed-off-by:
Victor Skvortsov <victor.skvortsov@amd.com> Reviewed-by:
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Jonathan Kim authored
If queue reset fails, tell the CP to reset the pipe. Since queues multiplex context per pipe and we've issued a device wide preemption prior to the hang, we can assume the hung pipe only has one queue to reset on pipe reset. Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Reviewed-by:
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Lijo Lazar authored
On EFI BIOSes, PCI ROM may be exported through EFI_PCI_IO_PROTOCOL and expansion ROM BARs may not be enabled. Choose to read from EFI exported ROM data before reading PCI Expansion ROM BAR. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
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