- 09 Apr, 2013 4 commits
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Arnd Bergmann authored
Merge tag 'ux500-pinctrl' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/drivers From Linus Walleij <linus.walleij@linaro.org>: ux500 pinctrl updates for the ARM SoC tree. * tag 'ux500-pinctrl' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson: ARM: ux500: 8500: add ab8500-musb pinctrl support ARM: ux500: remove redundant DB8500_PIN_SLEEP definition ARM: ux500: Add Snowball pin configuration for user LED ARM: ux500: u8500: fix pinctrl IDLE state definition for SPI2 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Arnd Bergmann authored
Merge tag 'tegra-for-3.10-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/drivers From Stephen Warren <swarren@wwwdotorg.org>: ARM: tegra: clock driver development This branch contains most fixes and enhancements to the Tegra common clock driver. The main new feature is a driver for Tegra114, which coupled with later device tree changes enables many devices on that chip, such as MMC, I2C, etc. This branch depends on a patch in: git://git.linaro.org/people/mturquette/linux.git clk-for-3.10 Mike has stated that this branch is stable, and is aware of this dependency and merge. Mike's branch is based on v3.9-rc3, which includes a USB change which causes problems on Tegra. That problem was fixed in v3.9-rc4. Hence, this branch pulls in v3.9-rc4 to ensure bisectability as much as possible. This branch is based on v3.9-rc4, followed by a merge of previous Tegra "soc" pull request, followed by a merge of clk-for-3.10. * tag 'tegra-for-3.10-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: clk: tegra: fix enum tegra114_clk to match binding clk: tegra: Remove forced clk_enable of uartd ARM: dt: Add references to tegra_car clocks clk: tegra: devicetree match for nvidia,tegra114-car clk: tegra: Implement clocks for Tegra114 ARM: tegra: Define Tegra114 CAR binding clk: tegra: Workaround for Tegra114 MSENC problem clk: tegra: Add flags to tegra_clk_periph() clk: tegra: Add new fields and PLL types for Tegra114 clk: tegra: move from a lock bit idx to a lock mask clk: tegra: Add PLL post divider table clk: tegra: introduce TEGRA_PLL_HAS_LOCK_ENABLE clk: tegra: Add TEGRA_PLL_BYPASS flag clk: tegra: Refactor PLL programming code clk: tegra: provide dummy cpu car ops clk: tegra: defer application of init table clk: tegra: Fix cdev1 and cdev2 IDs clk: tegra: Make gr2d and gr3d clocks children of pll_c clk: tegra: Export peripheral reset functions clk: tegra: Fix periph_clk_to_bit macro Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Arnd Bergmann authored
This is a snapshot of the stable clk branch at git://git.linaro.org/people/mturquette/linux.git clk-for-3.10 which is a dependency for the tegra clock changes. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Arnd Bergmann authored
This is a dependency for the tegra/clk branch. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Conflicts: drivers/clocksource/tegra20_timer.c
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- 08 Apr, 2013 6 commits
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Arnd Bergmann authored
Merge tag 'omap-for-v3.10/gpmc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers From Tony Lindgren <tony@atomide.com>: GPMC updates from Jon Hunter <jon-hunter@ti.com>: Adds GPMC (General Purpose Memory Controller) DT support for NOR flash and Ethernet and includes various GPMC cleans-up and fixes. This series is dependent on commit 71856843 (ARM: OMAP: use consistent error checking) from RMK's clean-up branch and commit 31d9adca (ARM: OMAP2+: Fix broken gpmc support). * tag 'omap-for-v3.10/gpmc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (29 commits) ARM: OMAP2+: Add GPMC DT support for Ethernet child nodes ARM: OMAP2+: rename gpmc_probe_nor_child() to gpmc_probe_generic_child() ARM: OMAP2+: return -ENODEV if GPMC child device creation fails ARM: OMAP2+: Allow GPMC probe to complete even if CS mapping fails ARM: OMAP2+: Remove unnecesssary GPMC definitions and variable ARM: OMAP2+: Detect incorrectly aligned GPMC base address ARM: OMAP2+: Convert ONENAND to retrieve GPMC settings from DT ARM: OMAP2+: Convert NAND to retrieve GPMC settings from DT ARM: OMAP2+: Add device-tree support for NOR flash ARM: OMAP2+: Add additional GPMC timing parameters ARM: OMAP2+: Add function to read GPMC settings from device-tree ARM: OMAP2+: Don't configure of chip-select options in gpmc_cs_configure() ARM: OMAP2+: Convert TUSB to use gpmc_cs_program_settings() ARM: OMAP2+: Convert SMC91x to use gpmc_cs_program_settings() ARM: OMAP2+: Convert NAND to use gpmc_cs_program_settings() ARM: OMAP2+: Convert ONENAND to use gpmc_cs_program_settings() ARM: OMAP2+: Add function for configuring GPMC settings ARM: OMAP2+: Add structure for storing GPMC settings ARM: OMAP2+: Add variable to store number of GPMC waitpins ARM: OMAP2+: Simplify code configuring ONENAND devices ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Arnd Bergmann authored
Merge tag 'omap-for-v3.10/timer-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers From Tony Lindgren <tony@atomide.com>: Clean-up for omap2+ timers from Jon Hunter <jon-hunter@ti.com>: This series consists mainly of clean-ups for clockevents and clocksource timers on OMAP2+ devices. The most significant change in functionality comes from the 5th patch which is changing the selection of the clocksource timer for OMAP3 and AM335x devices when gptimers are used for clocksource. Note that this series depends on 71856843 (ARM: OMAP: use consistent error checking) in RMK's tree and 960cba67 (ARM: OMAP5: timer: Update the clocksource name as per clock data) in omap-for-v3.10/fixes-non-critical. So this branch is based on a merge of 71856843 and omap-for-v3.10/fixes-non-critical to avoid non-trivial merge conflicts. * tag 'omap-for-v3.10/timer-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP4+: Fix sparse warning in system timers ARM: OMAP2+: Store ID of system timers in timer structure ARM: OMAP3: Update clocksource timer selection ARM: OMAP2+: Simplify system timers definitions ARM: OMAP2+: Simplify system timer clock definitions ARM: OMAP2+: Remove hard-coded test on timer ID ARM: OMAP2+: Display correct system timer name ARM: OMAP2+: fix typo "CONFIG_BRIDGE_DVFS" ARM: OMAP1: remove "config MACH_OMAP_HTCWIZARD" ARM: OMAP: dpll: enable bypass clock only when attempting dpll bypass ARM: OMAP2+: powerdomain: avoid testing whether an unsigned char is less than 0 ARM: OMAP2+: hwmod: Remove unused _HWMOD_WAKEUP_ENABLED flag ARM: OMAP2+: am335x: Change the wdt1 func clk src to per_32k clk ARM: OMAP2+: AM33xx: hwmod: Add missing sysc definition to wdt1 entry Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Arnd Bergmann authored
Merge tag 'omap-for-v3.10/usb-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers From Tony Lindgren <tony@atomide.com>: EHCI platform data related changes for v3.10 merge window. These are needed for the USB PHY support, and are based on commit 1f0972f5 from Felipe Balbi's tree as agreed on the mailing lists. * tag 'omap-for-v3.10/usb-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (21 commits) ARM: dts: omap3-beagle: Add USB Host support ARM: dts: OMAP3: Add HS USB Host IP nodes ARM: dts: OMAP4: Add HS USB Host IP nodes ARM: OMAP: zoom: Adapt to ehci-omap changes ARM: OMAP3: overo: Adapt to ehci-omap changes ARM: OMAP3: omap3touchbook: Adapt to ehci-omap changes ARM: OMAP3: omap3stalker: Adapt to ehci-omap changes ARM: OMAP3: omap3pandora: Adapt to ehci-omap changes ARM: OMAP3: omap3evm: Adapt to ehci-omap changes ARM: OMAP3: igep0020: Adapt to ehci-omap changes ARM: OMAP: devkit8000: Adapt to ehci-omap changes ARM: OMAP3: cm-t3517: Adapt to ehci-omap changes ARM: OMAP3: cm-t35: Adapt to ehci-omap changes ARM: OMAP: AM3517evm: Adapt to ehci-omap changes ARM: OMAP: AM3517crane: Adapt to ehci-omap changes ARM: OMAP3: 3630SDP: Adapt to ehci-omap changes ARM: OMAP3: 3430SDP: Adapt to ehci-omap changes ARM: OMAP3: Beagle: Adapt to ehci-omap changes ARM: OMAP2+: omap4panda: Adapt to ehci-omap changes ARM: OMAP2+: omap-usb-host: Add usbhs_init_phys() ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.xilinx.com/linux-xlnxArnd Bergmann authored
From Michal Simek <michal.simek@xilinx.com>: * 'zynq/clksrc/cleanup' of git://git.xilinx.com/linux-xlnx: arm: zynq: Move timer to generic location arm: zynq: Do not use xilinx specific function names arm: zynq: Move timer to clocksource interface arm: zynq: Use standard timer binding Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://server.prisktech.co.nz/git/linuxwmtArnd Bergmann authored
From Tony Prisk <linux@prisktech.co.nz>: arm: vt8500: Add pinctrl driver for arch-vt8500 This series adds support for the pinctrl/gpio module on all arch-vt8500 supported SoCs. As part of the review process, some tidy up is also done to drivers/of/base.c to remove some code that is being constantly duplicated. Also, a patch for the bcm2835 pinctrl driver is included to take advantage of the new of/base.c code. * tag 'vt8500/pinctrl' of git://server.prisktech.co.nz/git/linuxwmt: (606 commits) pinctrl: bcm2835: make use of of_property_read_u32_index() gpio: vt8500: Remove arch-vt8500 gpio driver arm: vt8500: Remove gpio devicetree nodes arm: dts: vt8500: Update Wondermedia SoC dtsi files for pinctrl driver pinctrl: gpio: vt8500: Add pincontrol driver for arch-vt8500 arm: vt8500: Increase available GPIOs on arch-vt8500 of: Remove duplicated code for validating property and value of: Add support for reading a u32 from a multi-value property. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Arnd Bergmann authored
Merge tag 'renesas-intc-external-irq2-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers From Simon Horman <horms+renesas@verge.net.au>: Update for Renesas INTC External IRQ pin driver for v3.10 This adds support for shared interrupt lines to the Renesas INTC External IRQ pin driver which has already been queued up for v3.10 (tag renesas-intc-external-irq-for-v3.10). * tag 'renesas-intc-external-irq2-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: irqchip: intc-irqpin: Add support for shared interrupt lines Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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- 05 Apr, 2013 1 commit
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Wei Yongjun authored
Remove duplicated include. Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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- 04 Apr, 2013 29 commits
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Stephen Warren authored
A gap exists in the binding's clock ID definitions. Fix the clock driver to be consistent. This allows pclk to be looked up through device tree and prevents: ERROR: could not get clock /pmc:pclk(0) Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Peter De Schrijver authored
The UART driver enables the console uart clock, so we don't need to do that anymore in this file. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Peter De Schrijver authored
Add references to tegra_car clocks for the basic device nodes. Also remove the clock-frequency property of the serial node as the UART driver can now use the clock framework to obtain the frequency. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Peter De Schrijver authored
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Peter De Schrijver authored
Implement clocks for Tegra114. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Peter De Schrijver authored
The device tree binding models Tegra114 CAR (Clock And Reset) as a single monolithic clock provider. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Peter De Schrijver authored
Workaround a hardware bug in MSENC during clock enable. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Peter De Schrijver authored
We will need some tegra peripheral clocks with the CLK_IGNORE_UNUSED flag, most notably mselect, which is a bridge between AXI and most peripherals. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Peter De Schrijver authored
Tegra114 introduces new PLL types. This requires new clocktypes as well as some new fields in the pll structure. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Peter De Schrijver authored
PLLC2 and PLLC3 on Tegra114 have separate phaselock and frequencylock bits. So switch to a lock mask to be able to test both at the same time. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Peter De Schrijver authored
Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider. Introduce a table based approach and switch PLLU to it. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Peter De Schrijver authored
Tegra114 PLLC2 and PLLC3 don't have a lock enable bit. The lock bits are always functional. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Peter De Schrijver authored
Not all PLLs in Tegra114 have a bypass bit. Adapt the common code to only use this bit when available. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Peter De Schrijver authored
Refactor the PLL programming code to make it useable by the new PLL types introduced by Tegra114. The following changes were done: * Split programming the PLL into updating m,n,p and updating cpcon * Move locking from _update_pll_cpcon() to clk_pll_set_rate() * Introduce _get_pll_mnp() helper * Move check for identical m,n,p values to clk_pll_set_rate() * struct tegra_clk_pll_freq_table will always contain the values as defined by the hardware. * Simplify the arguments to clk_pll_wait_for_lock() * Split _tegra_clk_register_pll() Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Peter De Schrijver authored
tegra_boot_secondary() relies on some of the car ops. This means having an uninitialized tegra_cpu_car_ops will lead to an early boot panic. Providing a dummy struct avoids this and makes adding Tegra114 clock support in a bisectable way a lot easier. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Stephen Warren authored
The Tegra clock driver is initialized during the ARM machine descriptor's .init_irq() hook. It can't be initialized earlier, since dynamic memory usage is required. It can't be initialized later, since the .init_timer() hook needs the clocks initialized. However, at this time, udelay() doesn't work. The Tegra clock initialization table may enable some PLLs. Enabling a PLL may require usage of udelay(). Hence, this can't happen right when the clock driver is initialized. To solve this, separate the clock driver initialization from the clock table processing, so they can execute at separate times. Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Prashant Gaikwad authored
Correct IDs for cdev1 and cdev2 are 94 and 93 respectively. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: split into separate driver and device-tree patches] Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Thierry Reding authored
By default these clocks are children of pll_m, but in downstream kernels they are reparented to pll_c. While at it, decrease their frequencies to 300 MHz because the defaults aren't in the specified range. gr2d can reportedly run at much higher frequencies, but 300 MHz works and is a more conservative default. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Thierry Reding authored
The tegra_periph_reset_assert() and tegra_periph_reset_deassert() functions can be used by drivers to reset peripherals. In order to allow such drivers to be built as modules, export the functions. Note that this restores the status quo as the functions were exported before the move to the drivers/clk tree. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Yen Lin authored
The parameter name should be "gate", not "periph". This worked, however, because it happens that everywhere periph_clk_to_bit is called, "gate" was in the local scope. Signed-off-by: Yen Lin <yelin@nvidia.com> Signed-off-by: Andrew Chew <achew@nvidia.com> Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Stephen Warren authored
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Stephen Warren authored
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git://github.com/jonhunter/linuxTony Lindgren authored
Merge branch 'omap-gpmc-for-v3.10-take2' of git://github.com/jonhunter/linux into omap-for-v3.10/gpmc
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Michal Simek authored
Move zynq timer out of mach folder to generic location and enable it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Michal Simek authored
Remove all xilinx specific names from the driver because this is generic driver for cadence ttc. xttc->ttc ttcps->ttc ... No functional changes in this driver. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Michal Simek authored
Use clocksource timer initialization. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Michal Simek authored
Use cdns,ttc because this driver is Cadence Rev06 Triple Timer Counter and everybody can use it without xilinx specific function name or probing. Also use standard dt description for timer and also prepare for moving to clocksource initialization. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Stephen Warren authored
Use the new standard API of_property_read_u32_index() instead of open- coding it. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
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Tony Prisk authored
With the move to a combined pinctrl/gpio driver, the arch-vt8500 gpio driver is no longer required. Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Acked-by: Linus Walleij <linus.walleij@linaro.org>
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