- 01 Jul, 2024 4 commits
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George Shen authored
[Why] Certain situations cause pipes to have a recout of 0, such as when the dst_rect lies completely outside of a given ODM slice. [How] Skip calculation that transforms cursor coordinates to viewport space. Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Signed-off-by:
Jerry Zuo <jerry.zuo@amd.com> Signed-off-by:
George Shen <george.shen@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Tom Chung authored
[Why] Sometimes the new_crtc_state->vrr_infopacket did not sync up with the current state. It will affect the update_freesync_state_on_stream() does not update the state correctly. [How] Reset the freesync config before get_freesync_config_for_crtc() to make sure we have the correct new_crtc_state for VRR. Reviewed-by:
Sun peng Li <sunpeng.li@amd.com> Signed-off-by:
Tom Chung <chiahsuan.chung@amd.com> Tested-by:
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Anthony Koo authored
- Add new Replay states 2A (initial Replay entry) and 4E (frame update) to check is there is new frame update before sending Acked-by:
Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by:
Anthony Koo <anthony.koo@amd.com> Tested-by:
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Alex Deucher authored
This is a big structure so use vmalloc as malloc can fail when there is memory pressure. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3454Reviewed-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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- 27 Jun, 2024 36 commits
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Mario Limonciello authored
Although designs may contain an ISP IP block, the camera might be a USB camera. Because of this the ISP firmware is considered optional from amdgpu. However if the firmware doesn't get loaded the hardware should not be initialized. Adjust the return code for early init to ensure the IP block doesn't go through the other init and fini sequences. Also decrease the message about firmware load failure to debug so it's not as alarming to users. Acked-by:
Pratap Nirujogi <pratap.nirujogi@amd.com> Signed-off-by:
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Yang Wang authored
refine isp firmware loading Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Pratap Nirujogi authored
Remove temporary WA to disable ISP prefetch as MMHUB SAW is initialized to support ISP HW access GART memory using the TLSi path with prefetch enabled. Signed-off-by:
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Pratap Nirujogi authored
snprintf can truncate the output fw filename if the isp ucode_prefix exceeds 29 characters. Knowing ISP ucode_prefix is in the format isp_x_x_x, limiting the size of ucode_prefix[] to 10 characters to fix the warning. Fixes the below warning: drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c: In function 'isp_early_init': drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c:192:58: warning: 'snprintf' output may be truncated before the last format character [-Wformat-truncation=] 192 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix); | ^ In function 'isp_load_fw_by_psp', inlined from 'isp_early_init' at drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c:218:8: drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c:192:9: note: 'snprintf' output between 12 and 41 bytes into a destination of size 40 192 | snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Reported-by:kernel test robot <lkp@intel.com> Reviewed-by:
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Pratap Nirujogi authored
Disable MMHUB prefetch for ISP v4.1.1 as a temporary WA until the GART supports MMHUB TLSi and SAW for ISP HW to access GART memory using the TLSi path. Reviewed-by:
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Pratap Nirujogi authored
Add independent IP centric modules for ISP4.1.0 and ISP4.1.1 hw blocks. Reviewed-by:
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Pratap Nirujogi authored
Map ISP IH interrupts to Linux generic IRQ for ISP driver to handle the interrupts using MFD IORESOURCE_IRQ resource. Reviewed-by:
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Alex Deucher authored
Add new config option and set proper dependencies for ISP. v2: add missed guards, drop separate Kconfig Reviewed-by:
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Pratap Nirujogi authored
Enable ISP for ISP V4.1.0 and V4.1.1 in amdgpu_discovery. Reviewed-by:
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Pratap Nirujogi authored
Add the isp driver in amdgpu to support ISP device on the APUs that supports ISP IP block. ISP hw block is used for camera front-end, pre and post processing operations. Reviewed-by:
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Pratap Nirujogi authored
ISP hw block is supported in some of the AMD GPU versions, add support to discover ISP IP in amdgpu_discovery. v2: squash in documentation update (Alex) Reviewed-by:
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Sonny Jiang authored
Add DPG support for JPEG 5.0 Signed-off-by:
Sonny Jiang <sonjiang@amd.com> Acked-by:
Saleemkhan Jamadar <saleemkhan.jamadar@amd.com> Reviewed-by:
David (Ming Qiang) Wu <David.Wu3@amd.com> Signed-off-by:
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Frank Min authored
Do not return failure for allocating GTT bo with dcc flag on gfx12. This will improve compatibility for UMD. Signed-off-by:
Frank Min <Frank.Min@amd.com> Reviewed-by:
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Aurabindo Pillai authored
Fixes a hang thats triggered when MPV is run on a DCN401 dGPU: mpv --hwdec=vaapi --vo=gpu --hwdec-codecs=all and then enabling fullscreen playback (double click on the video) The following calltrace will be seen: [ 181.843989] BUG: kernel NULL pointer dereference, address: 0000000000000000 [ 181.843997] #PF: supervisor instruction fetch in kernel mode [ 181.844003] #PF: error_code(0x0010) - not-present page [ 181.844009] PGD 0 P4D 0 [ 181.844020] Oops: 0010 [#1] PREEMPT SMP NOPTI [ 181.844028] CPU: 6 PID: 1892 Comm: gnome-shell Tainted: G W OE 6.5.0-41-generic #41~22.04.2-Ubuntu [ 181.844038] Hardware name: System manufacturer System Product Name/CROSSHAIR VI HERO, BIOS 6302 10/23/2018 [ 181.844044] RIP: 0010:0x0 [ 181.844079] Code: Unable to access opcode bytes at 0xffffffffffffffd6. [ 181.844084] RSP: 0018:ffffb593c2b8f7b0 EFLAGS: 00010246 [ 181.844093] RAX: 0000000000000000 RBX: 0000000000000000 RCX: 0000000000000004 [ 181.844099] RDX: ffffb593c2b8f804 RSI: ffffb593c2b8f7e0 RDI: ffff9e3c8e758400 [ 181.844105] RBP: ffffb593c2b8f7b8 R08: ffffb593c2b8f9c8 R09: ffffb593c2b8f96c [ 181.844110] R10: 0000000000000000 R11: 0000000000000000 R12: ffffb593c2b8f9c8 [ 181.844115] R13: 0000000000000001 R14: ffff9e3c88000000 R15: 0000000000000005 [ 181.844121] FS: 00007c6e323bb5c0(0000) GS:ffff9e3f85f80000(0000) knlGS:0000000000000000 [ 181.844128] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 181.844134] CR2: ffffffffffffffd6 CR3: 0000000140fbe000 CR4: 00000000003506e0 [ 181.844141] Call Trace: [ 181.844146] <TASK> [ 181.844153] ? show_regs+0x6d/0x80 [ 181.844167] ? __die+0x24/0x80 [ 181.844179] ? page_fault_oops+0x99/0x1b0 [ 181.844192] ? do_user_addr_fault+0x31d/0x6b0 [ 181.844204] ? exc_page_fault+0x83/0x1b0 [ 181.844216] ? asm_exc_page_fault+0x27/0x30 [ 181.844237] dcn20_get_dcc_compression_cap+0x23/0x30 [amdgpu] [ 181.845115] amdgpu_dm_plane_validate_dcc.constprop.0+0xe5/0x180 [amdgpu] [ 181.845985] amdgpu_dm_plane_fill_plane_buffer_attributes+0x300/0x580 [amdgpu] [ 181.846848] fill_dc_plane_info_and_addr+0x258/0x350 [amdgpu] [ 181.847734] fill_dc_plane_attributes+0x162/0x350 [amdgpu] [ 181.848748] dm_update_plane_state.constprop.0+0x4e3/0x6b0 [amdgpu] [ 181.849791] ? dm_update_plane_state.constprop.0+0x4e3/0x6b0 [amdgpu] [ 181.850840] amdgpu_dm_atomic_check+0xdfe/0x1760 [amdgpu] Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by:
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Ma Ke authored
In enable_phantom_plane, we should better check null pointer before accessing various structs. Fixes: 09a4ec5d ("drm/amd/display: Refactor dc_state interface") Signed-off-by:
Ma Ke <make24@iscas.ac.cn> Reviewed-by:
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Jane Jian authored
[WHY] sriov has the higher bit violation when flushing tlb [HOW] normalize the registers to keep lower 16-bit(dword aligned) to aviod higher bit violation RLCG will mask xcd out and always assume it's accessing its own xcd v2 add check in wait mem that only do the normalization on regspace Signed-off-by:
Jane Jian <Jane.Jian@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Acked-by:
Yiqing Yao <YiQing.Yao@amd.com> Signed-off-by:
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Aurabindo Pillai authored
Add some register offsets that are required for Display DCC on DCN401 Fixes: 2d072b44 ("drm/amd: Add reg definitions for DCN401 DCC") Reported-by:
Tom St Denis <tom.stdenis@amd.com> Signed-off-by:
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YiPeng Chai authored
Add gpu reset check and exception handling for page retirement. v2: Clear poison consumption messages cached in fifo after non mode-1 reset. Signed-off-by:
YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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YiPeng Chai authored
1. The poison fifo is only used for poison consumption requests. 2. Merge reset requests when poison fifo caches multiple poison consumption messages Signed-off-by:
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YiPeng Chai authored
In order to apply to the case where a large number of ras poison interrupts: 1. Change to use variable to record poison creation requests to avoid fifo full. 2. Prioritize handling poison creation requests instead of following the order of requests received by the driver. Signed-off-by:
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Vignesh Chander authored
For RAS error scenario, VF guest driver will check mailbox and set fed flag to avoid unnecessary HW accesses. additionally, poll for reset completion message first to avoid accidentally spamming multiple reset requests to host. v2: add another mailbox check for handling case where kfd detects timeout first v3: set host_flr bit and use wait_for_reset Signed-off-by:
Vignesh Chander <Vignesh.Chander@amd.com> Reviewed-by:
Zhigang Luo <Zhigang.Luo@amd.com> Signed-off-by:
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YiPeng Chai authored
Add variable to record the deferred error number read by driver. Signed-off-by:
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Vignesh Chander authored
So we can get clearer per device logging. Signed-off-by:
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Danijel Slivka authored
Why: Setting IH_RB_WPTR register to 0 will not clear the RB_OVERFLOW bit if RB_ENABLE is not set. How to fix: Set WPTR_OVERFLOW_CLEAR bit after RB_ENABLE bit is set. The RB_ENABLE bit is required to be set, together with WPTR_OVERFLOW_ENABLE bit so that setting WPTR_OVERFLOW_CLEAR bit would clear the RB_OVERFLOW. Signed-off-by:
Danijel Slivka <danijel.slivka@amd.com> Reviewed-by:
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Kenneth Feng authored
This reverts commit d3620eea. Revert this due to a final solution: commit ed3165d6 ("drm/amdgpu/jpeg5: reprogram doorbell setting after power up for each playback") Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
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Mario Limonciello authored
These have been announced so add them to the table. Acked-by:
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Mario Limonciello authored
These have been announced so add them to the table. Acked-by:
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Jiapeng Chong authored
Use existing swap() function rather than duplicating its implementation. ./drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c:1171:103-104: WARNING opportunity for swap(). ./drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c:1231:99-100: WARNING opportunity for swap(). Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=9400Signed-off-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by:
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Jiapeng Chong authored
The function are defined in the amdgpu_dm.c file, but not called anywhere, so delete the unused function. drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:371:20: warning: unused function 'reverse_planes_order'. Reported-by:
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Jiapeng Chong authored
Use of macro ARRAY_SIZE to calculate array size minimizes the redundant code and improves code reusability. ./drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c:164:45-46: WARNING: Use ARRAY_SIZE. ./drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c:183:47-48: WARNING: Use ARRAY_SIZE. ./drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c:237:45-46: WARNING: Use ARRAY_SIZE. ./drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c:257:47-48: WARNING: Use ARRAY_SIZE. Reported-by:
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Alex Deucher authored
Leftover copy pasta from original code. Reviewed-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Lijo Lazar authored
If reg list is already loaded on PSP 13.0.2 SOCs, psp will give TEE_ERR_CANCEL response on second time load. Avoid printing warn message for it. Signed-off-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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Julia Zhang authored
Instead of using state->fb->obj[0] directly, get object from framebuffer by calling drm_gem_fb_get_obj() and return error code when object is null to avoid using null object of framebuffer. Reported-by:
Fusheng Huang <fusheng.huang@ecarxgroup.com> Signed-off-by:
Julia Zhang <Julia.Zhang@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Hawking Zhang authored
adev->gfx.imu.funcs could be NULL Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Signed-off-by:
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Bob Zhou authored
Fix the unchecked return value warning reported by Coverity, so add error handling. Signed-off-by:
Bob Zhou <bob.zhou@amd.com> Reviewed-by:
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Aric Cyr authored
This version brings along the following: - Enable DCC on DCN401 - Add reg definitions for DCN401 DCC - Remove duplicate null check - Remove always true condition - Validate function returns - Ensure curve to hw translation succeed - Use periodic detection for ipx/headless - Fix 1DLUT setting for NL SDR blending - Adjust reg field for DSC wait for disconnect - Remove a redundant check in authenticated_dp - Add HW cursor visual confirm - Fix cursor issues with ODMs and magnification - Wait for double buffer update on ODM changes - Reset DSC memory status - Program CURSOR_DST_X_OFFSET in viewport space - Add null checks before accessing struct elements - Fix reduced resolution and refresh rate - Make DML2.1 P-State method force per stream - Add workaround to restrict max frac urgent for DPM0 - Call dpmm when checking mode support - resync OTG after DIO FIFO resync - Always enable HPO for DCN4 dGPU - Use sw cursor for DCN401 with rotation - Add Replay general cmd - Check HDCP returned status - Check and log for function error codes - Check and log for function error codes - Remove useless function call - Fix uninitialized variables in dcn401 - Fix cursor size issues - Run DC_LOG_DC after checking link->link_enc - Remove redundant checks for pipe_ctx->stream - Send DP_TOTAL_LTTPR_CNT during detection if LTTPR is present - Fix cursor issues with ODMs and HW rotations - Remove unnecessary variable - Remove redundant var from display_rq_dig_calc in dml - Refactor dccg401_get_other_enable_symclk_fe Acked-by:
Alex Hung <alex.hung@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
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