1. 07 Dec, 2016 12 commits
  2. 25 Nov, 2016 2 commits
    • Linus Walleij's avatar
      gpio: set explicit nesting on drivers · 35ca3f61
      Linus Walleij authored
      The ADNP, CrystalCove and WhiskeyCove are all nested GPIO
      irqchips, but were avoiding to connect the parent IRQ to
      the gpiochip. This works, but is kind of sloppy as the
      child IRQs are not marked as having the parent IRQ as
      parent.
      
      Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
      Cc: Ajay Thomas <ajay.thomas.david.rajamanickam@intel.com>
      Cc: Bin Gao <bin.gao@linux.intel.com>
      Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      35ca3f61
    • Linus Walleij's avatar
      gpio: simplify adding threaded interrupts · d245b3f9
      Linus Walleij authored
      This tries to simplify the use of CONFIG_GPIOLIB_IRQCHIP when
      using threaded interrupts: add a new call
      gpiochip_irqchip_add_nested() to indicate that we're dealing
      with a nested rather than a chained irqchip, then create a
      separate gpiochip_set_nested_irqchip() to mirror
      the gpiochip_set_chained_irqchip() call to connect the
      parent and child interrupts.
      
      In the nested case gpiochip_set_nested_irqchip() does nothing
      more than call irq_set_parent() on each valid child interrupt,
      which has little semantic effect in the kernel, but this is
      probably still formally correct.
      
      Update all drivers using nested interrupts to use
      gpiochip_irqchip_add_nested() so we can now see clearly
      which these users are.
      
      The DLN2 driver can drop its specific hack with
      .irq_not_threaded as we now recognize whether a chip is
      threaded or not from its use of gpiochip_irqchip_add_nested()
      signature rather than from inspecting .can_sleep.
      
      We rename the .irq_parent to .irq_chained_parent since this
      parent IRQ is only really kept around for the chained
      interrupt handlers.
      
      Cc: Lars Poeschel <poeschel@lemonage.de>
      Cc: Octavian Purdila <octavian.purdila@intel.com>
      Cc: Daniel Baluta <daniel.baluta@intel.com>
      Cc: Bin Gao <bin.gao@linux.intel.com>
      Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
      Cc: Ajay Thomas <ajay.thomas.david.rajamanickam@intel.com>
      Cc: Semen Protsenko <semen.protsenko@globallogic.com>
      Cc: Alexander Stein <alexander.stein@systec-electronic.com>
      Cc: Phil Reid <preid@electromag.com.au>
      Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com>
      Cc: Patrice Chotard <patrice.chotard@st.com>
      Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      d245b3f9
  3. 24 Nov, 2016 4 commits
  4. 22 Nov, 2016 4 commits
  5. 16 Nov, 2016 1 commit
  6. 15 Nov, 2016 3 commits
  7. 13 Nov, 2016 1 commit
  8. 12 Nov, 2016 1 commit
  9. 09 Nov, 2016 2 commits
  10. 04 Nov, 2016 1 commit
    • Paul Gortmaker's avatar
      gpio: htc-egpio: Make it explicitly non-modular · 43bbf94c
      Paul Gortmaker authored
      The Kconfig currently controlling compilation of this code is:
      
      drivers/gpio/Kconfig:config HTC_EGPIO
      drivers/gpio/Kconfig:   bool "HTC EGPIO support"
      
      ...meaning that it currently is not being built as a module by anyone.
      
      Lets remove the modular code that is essentially orphaned, so that
      when reading the driver there is no doubt it is builtin-only.
      
      We explicitly disallow a driver unbind, since that doesn't have a
      sensible use case anyway, and it allows us to drop the ".remove"
      code for non-modular drivers.
      
      Since module_init was not in use by this code, the init ordering
      remains unchanged with this commit.
      
      We also delete the MODULE_LICENSE tag etc. since all that information
      is already contained at the top of the file in the comments.
      
      Cc: Linus Walleij <linus.walleij@linaro.org>
      Cc: Alexandre Courbot <gnurou@gmail.com>
      Cc: Kevin O'Connor <kevin@koconnor.net>
      Cc: linux-gpio@vger.kernel.org
      Signed-off-by: default avatarPaul Gortmaker <paul.gortmaker@windriver.com>
      Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      43bbf94c
  11. 31 Oct, 2016 3 commits
  12. 25 Oct, 2016 2 commits
  13. 24 Oct, 2016 4 commits
    • Linus Walleij's avatar
    • Sascha Hauer's avatar
      gpio: mxs: fix duplicate level interrupts · f08ea3cc
      Sascha Hauer authored
      According to the reference manual level interrupts can't be acked
      using the IRQSTAT registers. The effect is that when a level interrupt
      triggers the following ack is a no-op and the same interrupt triggers
      again right after it has been unmasked after running the interrupt
      handler.
      
      The reference manual says:
      
      Status bits for pins configured as level sensitive interrupts cannot be
      cleared unless either the actual pin is in the non-interrupting state, or
      the pin has been disabled as an interrupt source by clearing its bit in
      HW_PINCTRL_PIN2IRQ.
      
      To work around the duplicated interrupts we can use the PIN2IRQ
      rather than the IRQEN registers to mask the interrupts. This
      probably does not work for the edge interrupts, so we have to split up
      the irq chip into two chip types, one for the level interrupts and
      one for the edge interrupts. We now make use of two different enable
      registers, so we have to take care to always enable the right one,
      especially during switching of the interrupt type. An easy way
      to accomplish this is to use the IRQCHIP_SET_TYPE_MASKED which
      makes sure that set_irq_type is called with masked interrupts. With this
      the flow to change the irq type is like:
      
      - core masks interrupt (using the current chip type)
      - mxs_gpio_set_irq_type() changes chip type if necessary
      - mxs_gpio_set_irq_type() unconditionally sets the enable bit in the
        now unused enable register
      - core eventually unmasks the interrupt (using the new chip type)
      Signed-off-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
      Reviewed-by: default avatarMarek Vasut <marex@denx.de>
      Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      f08ea3cc
    • Sascha Hauer's avatar
      gpio: mxs: use enable/disable regs to (un)mask irqs · 66a37c3b
      Sascha Hauer authored
      The mxs gpio controller does not only have a mask register to mask
      interrupts, but also enable/disable registers. Use the enable/disable
      registers rather than the mask register. This does not have any
      advantage for now, but makes the next patch simpler.
      Signed-off-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
      Reviewed-by: default avatarMarek Vasut <marex@denx.de>
      Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      66a37c3b
    • Mika Westerberg's avatar
      ACPI / gpio: Add support for naming GPIOs · 4035cc15
      Mika Westerberg authored
      Now that we have the new helper function that sets nice names for GPIO
      lines based on "gpio-line-names" device property, we can take advantage of
      this in acpi_gpiochip_add().
      Signed-off-by: default avatarMika Westerberg <mika.westerberg@linux.intel.com>
      Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
      4035cc15