- 28 Feb, 2019 4 commits
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Avri Altman authored
The busy timeout is 250msec per discard command. Signed-off-by:
Avri Altman <avri.altman@wdc.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Avri Altman authored
SD spec v5.1 adds discard support. The flows and commands are similar to mmc, so just set the discard arg in CMD38. A host which supports DISCARD shall check if the DISCARD_SUPPORT (b313) is set in the SD_STATUS register. If the card does not support discard, the host shall not issue DISCARD command, but ERASE command instead. Post the DISCARD operation, the card may de-allocate the discarded blocks partially or completely. So the host mustn't make any assumptions concerning the content of the discarded region. This is unlike ERASE command, in which the region is guaranteed to contain either '0's or '1's, depends on the content of DATA_STAT_AFTER_ERASE (b55) in the scr register. One more important difference compared to ERASE is the busy timeout which we will address on the next patch. Signed-off-by:
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BOUGH CHEN authored
After system suspend, CQE is in cqhci_off state, which set the HALT bit, make CQE in HALT state. If the SoC do not power down the USDHC module, then when system resume back, this bit keep the same, still set. Though there is a sdhci reset during sdhci_resume_host(), but this reset do not impact the CQE part, so need to clear this bit when enable CQE, otherwise CQE will stuck in the first CMDQ request after system resume back. Find this issue on NXP i.MX845s-mek board [ 105.919862] mmc2: cqhci: timeout for tag 6 [ 105.923965] mmc2: cqhci: ============ CQHCI REGISTER DUMP =========== [ 105.930407] mmc2: cqhci: Caps: 0x0000310a | Version: 0x00000510 [ 105.936847] mmc2: cqhci: Config: 0x00001001 | Control: 0x00000001 [ 105.943286] mmc2: cqhci: Int stat: 0x00000000 | Int enab: 0x00000006 [ 105.949725] mmc2: cqhci: Int sig: 0x00000006 | Int Coal: 0x00000000 [ 105.956164] mmc2: cqhci: TDL base: 0x7809b000 | TDL up32: 0x00000000 [ 105.962604] mmc2: cqhci: Doorbell: 0x00000040 | TCN: 0x00000000 [ 105.969043] mmc2: cqhci: Dev queue: 0x00000000 | Dev Pend: 0x00000000 [ 105.975483] mmc2: cqhci: Task clr: 0x00000000 | SSC1: 0x00011000 [ 105.981922] mmc2: cqhci: SSC2: 0x00000001 | DCMD rsp: 0x00000000 [ 105.988362] mmc2: cqhci: RED mask: 0xfdf9a080 | TERRI: 0x00000000 [ 105.994801] mmc2: cqhci: Resp idx: 0x00000000 | Resp arg: 0x00000000 [ 106.001240] mmc2: sdhci: ============ SDHCI REGISTER DUMP =========== [ 106.007680] mmc2: sdhci: Sys addr: 0xb2b37800 | Version: 0x00000002 [ 106.014120] mmc2: sdhci: Blk size: 0x00000200 | Blk cnt: 0x00000001 [ 106.020560] mmc2: sdhci: Argument: 0x00010000 | Trn mode: 0x00000013 [ 106.026999] mmc2: sdhci: Present: 0x01f88008 | Host ctl: 0x00000030 [ 106.033439] mmc2: sdhci: Power: 0x00000002 | Blk gap: 0x00000080 [ 106.039878] mmc2: sdhci: Wake-up: 0x00000008 | Clock: 0x0000000f [ 106.046318] mmc2: sdhci: Timeout: 0x0000008f | Int stat: 0x00000000 [ 106.052757] mmc2: sdhci: Int enab: 0x107f4000 | Sig enab: 0x107f4000 [ 106.059196] mmc2: sdhci: AC12 err: 0x00000000 | Slot int: 0x00000502 [ 106.065635] mmc2: sdhci: Caps: 0x07eb0000 | Caps_1: 0x8000b407 [ 106.072075] mmc2: sdhci: Cmd: 0x00000d1a | Max curr: 0x00ffffff [ 106.078514] mmc2: sdhci: Resp[0]: 0x00000900 | Resp[1]: 0x31360181 [ 106.084954] mmc2: sdhci: Resp[2]: 0x44473430 | Resp[3]: 0x00450100 [ 106.091392] mmc2: sdhci: Host ctl2: 0x00000008 [ 106.095836] mmc2: sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x7804b208 [ 106.102274] mmc2: sdhci: ============================================ [ 106.108785] mmc2: running CQE recovery Signed-off-by:
Haibo Chen <haibo.chen@nxp.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
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Chaotian Jing authored
the response type of CMD6 is R1B, when the first CMD6 gets response CRC error, do retry may get timeout error due to card may still in busy state, which cause this retry make no sense. Signed-off-by:
Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by:
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- 25 Feb, 2019 36 commits
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Ulf Hansson authored
The only user of mmc_align_data_size() is sdio_align_size(), which is called from SDIO func drivers to let them distinguish, how to optimally allocate data buffers. Let's move mmc_align_data_size() close to the SDIO code as to make it static, rename it to _sdio_align_size() and simplify its definition, all with the purpose of clarifying that this is SDIO specific. Signed-off-by:
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Ulf Hansson authored
MMC OF parsing functions, which parses various host DT properties, should stay close to each other. Therefore, let's move mmc_of_parse_voltage() close to mmc_of_parse() into host.c. Additionally, there is no reason to build the code only when CONFIG_OF is set, as there should be stub functions for the OF helpers that is being used, so let's drop this condition as well. Signed-off-by: -
Ulf Hansson authored
The only left user of mmc_regulator_get_ocrmask() is the mmc core itself. Therefore, let's drop the export and turn it into static. Signed-off-by: -
Ulf Hansson authored
The mmc regulator helper functions, are placed in the extensive core.c file. In a step towards trying to create a better structure of files, avoiding too many lines of code per file, let's move these helpers to a new file, regulator.c. Moreover, this within this context it makes sense to also drop the export of mmc_vddrange_to_ocrmask(), but instead let's make it internal to the mmc core. Signed-off-by: -
Ulf Hansson authored
Let's drop the open-coding of the parsing of the "voltage-ranges" DT property and convert to use the common mmc_of_parse_voltage() API instead. Signed-off-by: -
Ulf Hansson authored
All callers of mmc_wait_for_app_cmd() set the retries in-parameter to MMC_CMD_RETRIES. This is silly, so let's just drop the in-parameter altogether, as to simplify the code. Signed-off-by: -
Ulf Hansson authored
mmc_wait_for_app_cmd() is an internal function for sd_ops.c, thus let's drop the unnecessary export and turn it into static function. Signed-off-by: -
Takeshi Saito authored
SCC is used for SDR104/HS200/HS400. We need to change SCC_DT2FF according to the mode. If it is inappropriate, CRC error tends to occur. This adds variable "tap_hs400" for HS400 mode and configures SCC_DT2FF as needed. Signed-off-by:
Takeshi Saito <takeshi.saito.xv@renesas.com> [wsa: rebased to upstream and updated commit message] Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by:
Niklas Söderlund <niklas.soderlund@ragnatech.se> Tested-by:
Marek Vasut <marek.vasut@gmail.com> Signed-off-by:
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Ulf Hansson authored
The current approach with sending a CMD12 (STOP_TRANSMISSION) to complete a data transfer request, either because of using the open-ended transmission type or because of receiving an error during a pre-defined data transfer, isn't sufficient for the STM32 sdmmc variant. More precisely, this variant needs to clear the DPSM ("Data Path State Machine") by sending a CMD12, for all failing ADTC commands. Support this, by adding a struct mmc_command inside the struct mmci_host and initialize it to a CMD12 during ->probe(). Let's also add checks for the new conditions, to enable mmci_data_irq() and mmci_cmd_irq() to postpone the calls to mmci_request_end(), but instead send the CMD12. Cc: Ludovic Barre <ludovic.barre@st.com> Signed-off-by:Ludovic Barre <ludovic.barre@st.com>
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Gustavo A. R. Silva authored
In preparation to enabling -Wimplicit-fallthrough, mark switch cases according to what the compiler looks for, where we are expecting to fall through. Signed-off-by:
Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by:
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Thomas Petazzoni authored
The SDHCI core is know properly checking for the state of a WP GPIO, so there is no longer any need for the sdhci-tegra code to implement ->get_ro() using mmc_gpio_get_ro(). Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@bootlin.com> Tested-by:
Thierry Reding <treding@nvidia.com> Acked-by:
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Thomas Petazzoni authored
The SDHCI core is now properly checking for the state of a WP GPIO, so there is no longer any need for the sdhci-omap code to implement ->get_ro() using mmc_gpio_get_ro(). Signed-off-by:
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Thomas Petazzoni authored
Even though SDHCI controllers may have a dedicated WP pin that can be queried using the SDHCI_PRESENT_STATE register, some platforms may chose to use a separate regular GPIO to route the WP signal. Such a GPIO is typically represented using the wp-gpios property in the Device Tree. Unfortunately, the current sdhci_check_ro() function does not make use of such GPIO when available: it either uses a host controller specific ->get_ro() operation, or uses the SDHCI_PRESENT_STATE. Several host controller specific ->get_ro() functions are implemented just to check a WP GPIO state. Instead of pushing this to more controller-specific implementations, let's handle this in the core SDHCI code, just like it is already done for the CD GPIO in sdhci_get_cd(). The below patch simply changes sdhci_check_ro() to use the value of the WP GPIO if available. Signed-off-by:
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Linus Walleij authored
The WMT SDMMC driver uses slot GPIO helpers and does not make any use of <linux/gpio.h> so drop this surplus include. Cc: Tony Prisk <linux@prisktech.co.nz> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
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Linus Walleij authored
The Sunxi MMC driver uses slot GPIO helpers and does not make any use of <linux/gpio.h> or <linux/of_gpio.h> so drop these surplus includes. Cc: Chen-Yu Tsai <wens@csie.org> Cc: Andre Przywara <andre.przywara@arm.com> Cc: cenowy Zheng <icenowy@aosc.io> Acked-by:
Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by:
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Linus Walleij authored
The SDHCI PXAv2 driver uses slot GPIO helpers and does not make any use of <linux/gpio.h> so drop this surplus include. Cc: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by:
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Linus Walleij authored
The SDHCI BCM Kona driver uses slot GPIO helpers and does not make any use of <linux/gpio.h> or <linux/of_gpio.h> so drop these surplus includes. Cc: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by:
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Linus Walleij authored
The MXS-MMC driver uses slot GPIO helpers and does not make any use of <linux/gpio.h> or <linux/of_gpio.h> so drop these surplus includes. Cc: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by:
Fabio Estevam <festevam@gmail.com> Signed-off-by:
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Linus Walleij authored
The MXCMMC driver uses slot GPIO helpers and does not make any use of <linux/gpio.h> or <linux/of_gpio.h> so drop these surplus includes. Cc: Jun Qian <hangdianqj@163.com> Cc: Matteo Facchinetti <matteo.facchinetti@sirius-es.it> Signed-off-by:
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Colin Ian King authored
There is an if block that is not indented, fix this. Also add a break statement on the default case to clean up a cppcheck warning. Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Avri Altman authored
SD specs version 4.x and 5.x have a dedicated slices in the SCR register. Higher versions will rely on a combination of the existing fields. Signed-off-by:
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Avri Altman authored
In MMC, the discard arg is a read-only ext_csd parameter - set it once on card init. To be consistent, do that for SD as well even though its discard arg is always 0x0. Signed-off-by:
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Linus Walleij authored
The argument "override_active_level" made it possible to enforce a specific polarity on the write-protect GPIO line. All callers in the kernel pass "false" to this call after I have converted all drivers to use GPIO machine descriptors, so remove the argument and clean out this. This kind of polarity inversion should be handled by the GPIO descriptor inside the GPIO library if needed. This rids us of one instance of the kludgy calls into the gpiod_get_raw_value() API. Signed-off-by:
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Lukas Wunner authored
The BCM2835 MMC host driver sets the device's driver data pointer to NULL on ->remove() even though the driver core subsequently does the same in __device_release_driver(). Drop the duplicate assignment. Tested-by:
Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by:
Lukas Wunner <lukas@wunner.de> Cc: Frank Pavlic <f.pavlic@kunbus.de> Signed-off-by:
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Lukas Wunner authored
The BCM2835 MMC host driver uses a pointer to get from the private bcm2835_host structure to the generic mmc_host structure. However the latter is always immediately preceding the former in memory, so compute its address with a subtraction (which is cheaper than a dereference) and drop the superfluous pointer. No functional change intended. Signed-off-by:
Alexander Graf <agraf@suse.de> Signed-off-by:
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Lukas Wunner authored
bcm2835_add_host() invokes IS_ERR_OR_NULL() on a DMA channel pointer, however dma_request_slave_channel() (which was used to populate the pointer) never returns an error pointer. So a NULL pointer check is sufficient. Tested-by:
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Aaro Koskinen authored
When running OMAP1 kernel on QEMU, MMC access is annoyingly noisy: MMC: CTO of 0xff and 0xfe cannot be used! MMC: CTO of 0xff and 0xfe cannot be used! MMC: CTO of 0xff and 0xfe cannot be used! [ad inf.] Emulator warnings appear to be valid. The TI document SPRU680 [1] ("OMAP5910 Dual-Core Processor MultiMedia Card/Secure Data Memory Card (MMC/SD) Reference Guide") page 36 states that the maximum timeout is 253 cycles and "0xff and 0xfe cannot be used". Fix by using 0xfd as the maximum timeout. Tested using QEMU 2.5 (Siemens SX1 machine, OMAP310), and also checked on real hardware using Palm TE (OMAP310), Nokia 770 (OMAP1710) and Nokia N810 (OMAP2420) that MMC works as before. [1] http://www.ti.com/lit/ug/spru680/spru680.pdf Fixes: 730c9b7e ("[MMC] Add OMAP MMC host driver") Signed-off-by:Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by:
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Sowjanya Komatineni authored
This patch adds HW Command Queue for supported Tegra SDMMC controllers. Signed-off-by:
Sowjanya Komatineni <skomatineni@nvidia.com> Acked-by:
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Sowjanya Komatineni authored
Below are the supported DMA types in Host Control1 Register with Version 4 enable b'00 - SDMA b'01 - Not Used b'10 - ADMA2 b'11 - ADMA2 or ADMA3 ADMA3 uses Command Descriptor to issue an SD command. A multi-block data transfer is performed by using a pair of CMD descriptor and ADMA2 descriptor. ADMA3 performs multiple of multi-block data transfer by using Integrated Descriptor which is more suitable for Command Queuing to fetch both Command and Transfer descriptors. Host Capabilities register indicates the supports of ADMA3 DMA. Signed-off-by:
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Sowjanya Komatineni authored
Add supports-cqe optional property for MMC hosts. This property is used to identify the specific host controller supporting command queue. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Ulf Hansson authored
The git tree isn't used to maintain SDHCI, but instead we use the common MMC git tree. Let's drop it to avoid confusion. Signed-off-by:
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Ulf Hansson authored
The eMMC CQHCI is the host controller interface, introduced in the eMMC spec v5.1. The code was originally developed as collaboration among several people, however none really stepped in to maintain it. Let's add Adrian Hunter (Intel), Ritesh Harjani and Asutosh Das as the maintainers, whom knows both the code and the spec. Cc: Subhash Jadavani <subhashj@codeaurora.org> Signed-off-by:
Ritesh Harjani <riteshh@codeaurora.org> Acked-by:
Asutosh Das <asutoshd@codeaurora.org>
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Nicolas Ferre authored
This patch adds support for 8-bit buswidth. Relevant SDCR value modified. Signed-off-by:
Nicolas Ferre <nicolas.ferre@microchip.com> Reviewed-by:
Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by:
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Takeshi Saito authored
This fixes card initialization failure in high speed mode. If U-Boot uses SDR or HS200/400 mode before starting Linux and Linux DT does not enable SDR/HS200/HS400 mode, card initialization fails in high speed mode. It is necessary to initialize SCC registers during card initialization phase. HW reset function is registered only for a port with either of SDR/HS200/HS400 properties in device tree. If SDR/HS200/HS400 properties are not present in device tree, SCC registers will not be reset. In SoC that support SCC registers, HW reset function should be registered regardless of the configuration of device tree. Reproduction procedure: - Use U-Boot that support MMC HS200/400 mode. - Delete HS200/HS400 properties in device tree. (Delete mmc-hs200-1_8v and mmc-hs400-1_8v) - MMC port works high speed mode and all commands fail. Signed-off-by:
Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Cc: Simon Horman <horms+renesas@verge.net.au> Reviewed-by:
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Paul Cercueil authored
Drop the custom code to get the 'cd' and 'wp' GPIOs. The driver now calls mmc_of_parse() which will init these from devicetree or device properties. Also drop the custom code to get the 'power' GPIO. The MMC core provides us with the means to power the MMC card through an external regulator. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Reviewed-by:
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Ernest Zhang(WH) authored
O2 SD host controller only need set the quirk2 flag SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD when work on force 1.8v emmc mode but not normal mode Signed-off-by:
Ernest Zhang <ernest.zhang@bayhubtech.com> Acked-by:
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