1. 07 Mar, 2018 6 commits
  2. 01 Mar, 2018 1 commit
    • Thomas Gleixner's avatar
      x86/cpu_entry_area: Sync cpu_entry_area to initial_page_table · 945fd17a
      Thomas Gleixner authored
      The separation of the cpu_entry_area from the fixmap missed the fact that
      on 32bit non-PAE kernels the cpu_entry_area mapping might not be covered in
      initial_page_table by the previous synchronizations.
      
      This results in suspend/resume failures because 32bit utilizes initial page
      table for resume. The absence of the cpu_entry_area mapping results in a
      triple fault, aka. insta reboot.
      
      With PAE enabled this works by chance because the PGD entry which covers
      the fixmap and other parts incindentally provides the cpu_entry_area
      mapping as well.
      
      Synchronize the initial page table after setting up the cpu entry
      area. Instead of adding yet another copy of the same code, move it to a
      function and invoke it from the various places.
      
      It needs to be investigated if the existing calls in setup_arch() and
      setup_per_cpu_areas() can be replaced by the later invocation from
      setup_cpu_entry_areas(), but that's beyond the scope of this fix.
      
      Fixes: 92a0f81d ("x86/cpu_entry_area: Move it out of the fixmap")
      Reported-by: default avatarWoody Suwalski <terraluna977@gmail.com>
      Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
      Tested-by: default avatarWoody Suwalski <terraluna977@gmail.com>
      Cc: William Grant <william.grant@canonical.com>
      Cc: stable@vger.kernel.org
      Link: https://lkml.kernel.org/r/alpine.DEB.2.21.1802282137290.1392@nanos.tec.linutronix.de
      945fd17a
  3. 28 Feb, 2018 2 commits
  4. 23 Feb, 2018 2 commits
  5. 21 Feb, 2018 19 commits
  6. 20 Feb, 2018 9 commits
  7. 17 Feb, 2018 1 commit
    • Dominik Brodowski's avatar
      x86/entry/64: Use 'xorl' for faster register clearing · ced5d0bf
      Dominik Brodowski authored
      On some x86 CPU microarchitectures using 'xorq' to clear general-purpose
      registers is slower than 'xorl'. As 'xorl' is sufficient to clear all
      64 bits of these registers due to zero-extension [*], switch the x86
      64-bit entry code to use 'xorl'.
      
      No change in functionality and no change in code size.
      
      [*] According to Intel 64 and IA-32 Architecture Software Developer's
          Manual, section 3.4.1.1, the result of 32-bit operands are "zero-
          extended to a 64-bit result in the destination general-purpose
          register." The AMD64 Architecture Programmer’s Manual Volume 3,
          Appendix B.1, describes the same behaviour.
      Suggested-by: default avatarDenys Vlasenko <dvlasenk@redhat.com>
      Signed-off-by: default avatarDominik Brodowski <linux@dominikbrodowski.net>
      Cc: Andy Lutomirski <luto@kernel.org>
      Cc: Arjan van de Ven <arjan@linux.intel.com>
      Cc: Borislav Petkov <bp@alien8.de>
      Cc: Dan Williams <dan.j.williams@intel.com>
      Cc: Dave Hansen <dave.hansen@linux.intel.com>
      Cc: David Woodhouse <dwmw2@infradead.org>
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Cc: Josh Poimboeuf <jpoimboe@redhat.com>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Link: http://lkml.kernel.org/r/20180214175924.23065-3-linux@dominikbrodowski.net
      [ Improved on the changelog a bit. ]
      Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
      ced5d0bf