- 18 Apr, 2023 2 commits
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Srinivas Goud authored
Currently SPI Cadence controller works only in Master mode. Updated interrupt handler for Full duplex transfer in Slave mode. Interrupt handler rely on the TX empty interrupt even for Slave mode transfer due to below HW limitation. HW limitation: AR 65885 - SPI Controller Might Not Update RX_NEMPTY Flag, Showing Incorrect Status Of The Receive FIFO SPI Slave mode works in the following manner: 1. One transfer can be finished only after all transfer->len data been transferred to master device. 2. Slave device only accepts transfer->len data. Any data longer than this from master device will be dropped. Any data shorter than this from master will cause SPI to be stuck due to the above behavior. 3. The stale data present in RXFIFO will be dropped in unprepared hardware transfer function. Signed-off-by:
Srinivas Goud <srinivas.goud@amd.com> Link: https://lore.kernel.org/r/1681825625-10265-3-git-send-email-srinivas.goud@amd.comSigned-off-by:
Mark Brown <broonie@kernel.org>
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Srinivas Goud authored
Replace spi_master structure with spi_controller structure. spi_controller structure provides interface support for both SPI master and slave controller. Signed-off-by:
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- 17 Apr, 2023 5 commits
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Mark Brown authored
Merge series from Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>: Update Xilinx Versal external DMA read logic to fix random issues - Instead of having the fixed timeout, update the read timeout based on the length of the transfer to avoid timeout for larger data size. - While switching between external DMA read and indirect read, disable the SPI before configuration and enable it after configuration as recommended by Octal-SPI Flash Controller specification. Sai Krishna Potthuri (2): spi: cadence-quadspi: Update the read timeout based on the length spi: cadence-quadspi: Disable the SPI before reconfiguring drivers/spi/spi-cadence-quadspi.c | 40 ++++++++++++++++++------------- 1 file changed, 24 insertions(+), 16 deletions(-) -- 2.25.1
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Brad Larson authored
The AMD Pensando Elba SoC includes a DW apb_ssi v4 controller with device specific chip-select control. The Elba SoC provides four chip-selects where the native DW IP supports two chip-selects. The Elba DW_SPI instance has two native CS signals that are always overridden. Signed-off-by:
Brad Larson <blarson@amd.com> Reviewed-by:
Serge Semin <fancer.lancer@gmail.com> Link: https://lore.kernel.org/r/20230410184526.15990-11-blarson@amd.comSigned-off-by:
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Brad Larson authored
The AMD Pensando Elba SoC has integrated the DW APB SPI Controller Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
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Sai Krishna Potthuri authored
Observed random DMA timeout failures while doing back to back transfers which involves switching the modes from DMA to NON-DMA. This issue is observed while testing the OSPI+UBIFS file system test case where rootfs is mounted from OSPI UBIFS partition. To avoid this issue, disable the SPI before changing the configuration from external DMA to NON-DMA and vice versa and reenable it after changing the configuration. As per the Cadence Octal SPI design specification, it is recommended to disable the Octal-SPI enable bit before reconfiguring. Signed-off-by:
Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> Link: https://lore.kernel.org/r/20230320095931.2651714-3-sai.krishna.potthuri@amd.comSigned-off-by:
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Sai Krishna Potthuri authored
When performing indirect read via external DMA the timeout for completion is set equal to the read length instead of fixed timeout value. For reads larger than 500 bytes, the timeout will continue to be equal to the read length whereas for a small read like the Read Status Register command, the timeout would be 1 or 2 milliseconds. This is not enough to cover the overhead needed in setting up DMA, in that case make sure the timeout is at least 500ms to allow DMA to finish. This solution is inline with the timeout used for Direct read via DMA. Signed-off-by:
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- 13 Apr, 2023 1 commit
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Rohit Ner authored
SPI test framework is designed to run each test case for a list of lengths. Introduce a module parameter to limit the iterations to a single value among the list of lengths. Signed-off-by:
Rohit Ner <rohitner@google.com> Link: https://lore.kernel.org/r/20230412202009.3750955-2-rohitner@google.comSigned-off-by:
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- 11 Apr, 2023 2 commits
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Martin Kurbanov authored
This is a driver for the Amlogic SPI flash controller support on A113L SoC. Signed-off-by:
Martin Kurbanov <mmkurbanov@sberdevices.ru> Reviewed-by:
Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230403183217.13280-3-mmkurbanov@sberdevices.ruSigned-off-by:
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Martin Kurbanov authored
Add YAML devicetree Amlogic A1 (A113L SoC) SPIFC. Signed-off-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230403183217.13280-2-mmkurbanov@sberdevices.ruSigned-off-by:
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- 05 Apr, 2023 9 commits
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Mark Brown authored
Merge series from Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>: This patch series fixes the following bugs in spi-pci1xxxx driver: 1. Length of SPI transactions is improper 2. SPI transactions fail after suspend and resume 3. Incorrect implementation of pci1xxxx_spi_set_cs API
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Christophe Leroy authored
The verification is already do in the SPI core by function __spi_validate(), not it to check it again in fsl_spi_bufs(). Signed-off-by:
Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/9ace69a8085e22fafd9159e99edd7bbfae2f9940.1680371809.git.christophe.leroy@csgroup.euSigned-off-by:
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Christophe Leroy authored
mspi_apply_cpu_mode_quirks() always returns the passed bits_per_word unmodified. Make it return void, then don't check bits_per_word anymore on return as it doesn't change. bits_per_word is already checked by __spi_validate() so no risk to have bits_per_word higher than 32. Signed-off-by:
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Christophe Leroy authored
On CPM, the RISC core is a lot more efficiant when doing transfers in 16-bits chunks than in 8-bits chunks, but unfortunately the words need to be byte swapped as seen in a previous commit. So, for large tranfers with an even size, allocate a temporary tx buffer and byte-swap data before and after transfer. This change allows setting higher speed for transfer. For instance on an MPC 8xx (CPM1 comms RISC processor), the documentation tells that transfer in byte mode at 1 kbit/s uses 0.200% of CPM load at 25 MHz while a word transfer at the same speed uses 0.032% of CPM load. This means the speed can be 6 times higher in word mode for the same CPM load. For the time being, only do it on CPM1 as there must be a trade-off between the CPM load reduction and the CPU load required to byte swap the data. Signed-off-by:
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Christophe Leroy authored
For different reasons, fsl-spi driver performs bits_per_word modifications for different reasons: - On CPU mode, to minimise amount of interrupts - On CPM/QE mode to work around controller byte order For CPU mode that's done in fsl_spi_prepare_message() while for CPM mode that's done in fsl_spi_setup_transfer(). Reunify all of it in fsl_spi_prepare_message(), and catch impossible cases early through master's bits_per_word_mask instead of returning EINVAL later. Signed-off-by:
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Christophe Leroy authored
CPM has the same problem as QE so for CPM also use the fix added by commit 0398fb70 ("spi/spi_mpc8xxx: Fix QE mode Litte Endian"): CPM mode uses Little Endian so words > 8 bits are byte swapped. Workaround this by always enforcing wordsize 8 for 16 and 32 bits words. Unfortunately this will not work for LSB transfers where wordsize is > 8 bits so disable these for now. Also limit the workaround to 16 and 32 bits words because it can only work for multiples of 8-bits. Signed-off-by:
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Tharun Kumar P authored
Hardware does not have support to disable individual chip select lines. Disable all chip select lines by using SPI_FORCE_CE bit. Fixes: 1cc0cbea ("spi: microchip: pci1xxxx: Add driver for SPI controller of PCI1XXXX PCIe switch") Signed-off-by:
Tharun Kumar P <tharunkumar.pasumarthi@microchip.com> Link: https://lore.kernel.org/r/20230404171613.1336093-4-tharunkumar.pasumarthi@microchip.comSigned-off-by:
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Tharun Kumar P authored
pci1xxxx_spi_resume API masks SPI interrupt bit which prohibits interrupt from coming to the host at the end of the transaction after suspend-resume. This patch unmasks this bit at resume. Fixes: 1cc0cbea ("spi: microchip: pci1xxxx: Add driver for SPI controller of PCI1XXXX PCIe switch") Signed-off-by:
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Tharun Kumar P authored
In pci1xxxx_spi_transfer_one API, length of SPI transaction gets cleared by setting of length mask. Set length of transaction only after masking length field. Fixes: 1cc0cbea ("spi: microchip: pci1xxxx: Add driver for SPI controller of PCI1XXXX PCIe switch") Signed-off-by:
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- 04 Apr, 2023 8 commits
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Mark Brown authored
Merge series from Uwe Kleine-König <u.kleine-koenig@pengutronix.de>: After fixing the error handling in the .remove() callback of the qup driver, convert it to .remove_new() preparing to make platform driver's remove functions return void.
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Uwe Kleine-König authored
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by:
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20230330210341.2459548-3-u.kleine-koenig@pengutronix.deSigned-off-by:
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Yang Li authored
According to commit 890cc39a ("drivers: provide devm_platform_get_and_ioremap_resource()"), convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by:
Yang Li <yang.lee@linux.alibaba.com> Link: https://lore.kernel.org/r/20230328061031.70140-2-yang.lee@linux.alibaba.comSigned-off-by:
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Yang Li authored
According to commit 890cc39a ("drivers: provide devm_platform_get_and_ioremap_resource()"), convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by:
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Yang Li authored
According to commit 890cc39a ("drivers: provide devm_platform_get_and_ioremap_resource()"), convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by:
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Yang Li authored
According to commit 890cc39a ("drivers: provide devm_platform_get_and_ioremap_resource()"), convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by:
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Kevin Groeneveld authored
When using gpio based chip select the cs value can go outside the range 0 – 3. The various MX51_ECSPI_* macros did not take this into consideration resulting in possible corruption of the configuration. For example for any cs value over 3 the SCLKPHA bits would not be set and other values in the register possibly corrupted. One way to fix this is to just mask the cs bits to 2 bits. This still allows all 4 native chip selects to work as well as gpio chip selects (which can use any of the 4 chip select configurations). Signed-off-by:
Kevin Groeneveld <kgroeneveld@lenbrook.com> Link: https://lore.kernel.org/r/20230318222132.3373-1-kgroeneveld@lenbrook.comSigned-off-by:
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Uwe Kleine-König authored
Returning early in a platform driver's remove callback is wrong. In this case the dma resources are not released in the error path. this is never retried later and so this is a permanent leak. To fix this, only skip hardware disabling if waking the device fails. Fixes: 64ff247a ("spi: Add Qualcomm QUP SPI controller support") Signed-off-by:
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- 31 Mar, 2023 2 commits
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Mika Westerberg authored
Intel Meteor Lake-S has the same SPI serial flash controller as Meteor Lake-P. Add Meteor Lake-S PCI ID to the driver list of supported devices. Signed-off-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20230331052812.39983-1-mika.westerberg@linux.intel.comSigned-off-by:
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Uwe Kleine-König authored
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Convert this driver from always returning zero in the remove callback to the void returning variant. Now that bcm2835_spi_remove returns no error code any more, bcm2835_spi_shutdown() does the same thing as bcm2835_spi_remove(). So drop the shutdown function and use bcm2835_spi_remove() as .shutdown callback. Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20230330211022.2460233-1-u.kleine-koenig@pengutronix.deSigned-off-by:
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- 30 Mar, 2023 1 commit
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Jaewon Kim authored
This patch adds missing variable no_cs descriptions. Signed-off-by:
Jaewon Kim <jaewon02.kim@samsung.com> Reviewed-by:
Andi Shyti <andi@etezian.org> Link: https://lore.kernel.org/r/20230306014239.80570-1-jaewon02.kim@samsung.comSigned-off-by:
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- 29 Mar, 2023 1 commit
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Yang Li authored
Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_ioremap_resource(), as this is exactly what this function does. Signed-off-by:
Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20230329062450.58924-1-yang.lee@linux.alibaba.comSigned-off-by:
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- 28 Mar, 2023 2 commits
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Yang Li authored
According to commit 890cc39a ("drivers: provide devm_platform_get_and_ioremap_resource()"), convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by:
Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/20230328061524.77529-1-yang.lee@linux.alibaba.comSigned-off-by:
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Douglas Anderson authored
It's fairly common practice for drivers to switch to a "sleep" pinctrl state at the end of its runtime_suspend function and then back to "default" at the beginning of runtime_resume. Let's do that for spi-qcom-qspi. Signed-off-by:
Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20230323102605.5.I79544b9486033bd7b27f2be55adda6d36f62a366@changeidSigned-off-by:
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- 27 Mar, 2023 5 commits
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Yang Li authored
According to commit 890cc39a ("drivers: provide devm_platform_get_and_ioremap_resource()"), convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by:
Baolin Wang <baolin.wang@linux.alibaba.com> Link: https://lore.kernel.org/r/20230327060516.93509-2-yang.lee@linux.alibaba.comSigned-off-by:
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Yang Li authored
According to commit 890cc39a ("drivers: provide devm_platform_get_and_ioremap_resource()"), convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by:
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Yang Li authored
According to commit 890cc39a ("drivers: provide devm_platform_get_and_ioremap_resource()"), convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by:
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Yang Li authored
According to commit 890cc39a ("drivers: provide devm_platform_get_and_ioremap_resource()"), convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by:
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Yang Li authored
According to commit 890cc39a ("drivers: provide devm_platform_get_and_ioremap_resource()"), convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by:
Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20230327055346.76625-1-yang.lee@linux.alibaba.comSigned-off-by:
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- 22 Mar, 2023 2 commits
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Kunihiko Hayashi authored
The .supports_op() callback function returns true by default after performing driver-specific checks. Therefore the driver cannot apply the buswidth in devicetree. Call spi_mem_default_supports_op() helper to handle the buswidth in devicetree. Fixes: 1b74dd64 ("spi: Add Socionext F_OSPI SPI flash controller driver") Signed-off-by:
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20230322023101.24490-1-hayashi.kunihiko@socionext.comSigned-off-by:
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Haibo Chen authored
When clock rate > 100MHz, use the DLL calibration mode, and finally add the suggested half of the current clock cycle to sample the data. Signed-off-by:
Haibo Chen <haibo.chen@nxp.com> Link: https://lore.kernel.org/r/20230322090451.3179431-2-haibo.chen@nxp.comSigned-off-by:
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