- 16 May, 2011 1 commit
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Andy Lutomirski authored
Loading fpu without aesni-intel does nothing. Loading aesni-intel without fpu causes modes like xts to fail. (Unloading aesni-intel will restore those modes.) One solution would be to make aesni-intel depend on fpu, but it seems cleaner to just combine the modules. This is probably responsible for bugs like: https://bugzilla.redhat.com/show_bug.cgi?id=589390Signed-off-by:
Andy Lutomirski <luto@mit.edu> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
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- 11 May, 2011 10 commits
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Phil Sutter authored
This also makes the dummy scatterlist in mv_hash_final() needless, so drop it. XXX: should this routine be made pulicly available? There are probably other users with their own implementations. Signed-off-by:
Phil Sutter <phil.sutter@viprinet.com> Signed-off-by:
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Phil Sutter authored
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Phil Sutter authored
On one hand, the digest state registers need to be set only when actually using the crypto engine. On the other hand, there is a check for ctx->first_hash in mv_process_hash_current() already, so use that. Signed-off-by:
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Phil Sutter authored
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Phil Sutter authored
The main goal was to have it not do anything when a zero len parameter was being passed (which could lead to a null pointer dereference, as in this case p->src_sg is null, either). Using the min() macro, the lower part of the loop gets simpler, too. Signed-off-by:
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Phil Sutter authored
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Phil Sutter authored
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Phil Sutter authored
The code in mv_hash_final is actually a superset of mv_hash_finup's body. Since the driver works fine without, drop it. Signed-off-by:
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Phil Sutter authored
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Phil Sutter authored
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- 04 May, 2011 12 commits
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Kim Phillips authored
during recent descriptor development, an Invalid Sequence Command error triggered a: BUG: recent printk recursion! due to insufficient memory allocated for the error text. The Invalid Sequence Command error text is the longest. The length of the maximum error string is computed as the sum of: "DECO: ": 6 "jump tgt desc idx 255: ": 23 Invalid Sequence Command text: 272 zero termination character: 1 i.e, 302 characters. Define this maximum error string length in error.h and fix caam_jr_strstatus callsites. Signed-off-by:
Kim Phillips <kim.phillips@freescale.com> Signed-off-by:
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Kim Phillips authored
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Dmitry Eremin-Solenikov authored
PPC 970FX Evaluation kit (Maple) boards bear AMD8111 southbridge. Allow this driver to be compiled in if PPC_MAPLE is selected. Signed-off-by:
Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Acked-by:
Matt Mackall <mpm@selenic.com> Signed-off-by:
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Dmitry Eremin-Solenikov authored
As amd driver doesn't bind to PCI device, we'd better manage reource allocation on our own to disallow (possible) conflicts. Signed-off-by:
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Gerald Schaefer authored
This patch adds System z hardware acceleration support for AES, DES and 3DES in CTR mode. The hardware support is available starting with System z196. Signed-off-by:
Gerald Schaefer <gerald.schaefer@de.ibm.com> Signed-off-by:
Jan Glauber <jang@linux.vnet.ibm.com> Signed-off-by:
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Jan Glauber authored
Add the CTR mode speed test for AES. Signed-off-by:
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Jan Glauber authored
Cleanup the remaining s390 crypto options by mentioning the earliest machine type that supports an accelerated algorithm. Signed-off-by:
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Gerald Schaefer authored
This patch adds System z hardware acceleration support for the GHASH algorithm for GCM (Galois/Counter Mode). The hardware support is available beginning with System z196. Signed-off-by:
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Gerald Schaefer authored
This patch adds System z hardware acceleration support for the AES XTS mode. The hardware support is available beginning with System z196. Signed-off-by:
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Jan Glauber authored
Remove a stale file left over from 1efbd15c and and cleanup the DES code a bit to make it easier to add new code. Signed-off-by:
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Jan Glauber authored
The specification which crypto facility is required for an algorithm is added as a parameter to the availability check which is done before an algorithm is registered. With this change it is easier to add new algorithms that require different facilities. Signed-off-by:
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Puneet Saxena authored
the fix add testcase for testing aes ofb mode. Signed-off-by:
Puneet Saxena <puneets@nvidia.com> Signed-off-by:
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- 02 May, 2011 4 commits
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Kim Phillips authored
keep the hex error value reporting version (a) to be consistent with decrypt_done(), and (b) to keep our hardware guys happy. Signed-off-by:
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Kim Phillips authored
remains from descriptor debugging - not required for normal operation. Signed-off-by:
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Kim Phillips authored
The presence of a h/w Queue Interface would fail due to this cut-n-paste snafu. Signed-off-by:
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Kim Phillips authored
- add IRQF_SHARED to request_irq flags to support parts such as the p1023 that has one IRQ line per couple of rings. - resetting a job ring triggers an interrupt, so move request_irq prior to jr_reset to avoid 'got IRQ but nobody cared' messages. - disable IRQs in h/w to avoid contention between reset and interrupt status - delete invalid comment - if there were incomplete jobs, module would be in use, preventing an unload. Signed-off-by:
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- 26 Apr, 2011 4 commits
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Dmitry Kasatkin authored
This patch fixes 2 hmac inter-dependent bugs. 1. "omap-sham: hash-in-progress is stored in hw format" commit introduced optimization where temporary hash had been stored in OMAP specific format (big endian). For SHA1 it is different to real hash format, which is little endian. Final HMAC value was calculated using incorrect hash. Because CONFIG_CRYPTO_MANAGER_TESTS was disabled this error remained unnoticed. After enabling this option, bug has been found. 2. HMAC was calculated using temporrary hash value. For a single-request updates, temporary hash was the final one and HMAC result was correct. But in fact only the final hash had to be used. All crypto tests for HMAC produces only single request and could not catch the problem. This problem is fixed here. Signed-off-by:
Dmitry Kasatkin <dmitry.kasatkin@nokia.com> Signed-off-by:
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Dmitry Kasatkin authored
EMU chips also have crypto HW as HS chips. Signed-off-by:
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Dmitry Kasatkin authored
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Markku Kylanpaa authored
SHA1 accelerator can also be busy. Add -EBUSY status return option and return busy status from omap_sham_finup(). Signed-off-by:
Markku Kylanpaa <ext-markku.kylanpaa@nokia.com> Signed-off-by:
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- 08 Apr, 2011 2 commits
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Vladimir Zapolskiy authored
This change adds support for AES encrypting and decrypting using advanced crypto engine found on Samsung S5PV210 and S5PC110 SoCs. Signed-off-by:
Vladimir Zapolskiy <vzapolskiy@gmail.com> Signed-off-by:
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Julia Lawall authored
Error handling code following a kmalloc should free the allocated data. The semantic match that finds the problem is as follows: (http://www.emn.fr/x-info/coccinelle/) // <smpl> @r exists@ local idexpression x; statement S; expression E; identifier f,f1,l; position p1,p2; expression *ptr != NULL; @@ x@p1 = \(kmalloc\|kzalloc\|kcalloc\)(...); ... if (x == NULL) S <... when != x when != if (...) { <+...x...+> } ( x->f1 = E | (x->f1 == NULL || ...) | f(...,x->f1,...) ) ...> ( return \(0\|<+...x...+>\|ptr\); | return@p2 ...; ) @script:python@ p1 << r.p1; p2 << r.p2; @@ print "* file: %s kmalloc %s return %s" % (p1[0].file,p1[0].line,p2[0].line) // </smpl> Signed-off-by:
Julia Lawall <julia@diku.dk> Acked-by:
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- 27 Mar, 2011 7 commits
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Jamie Iles authored
The SPAcc's have 2 equally sized FIFO's - a command FIFO and a status FIFO. The command FIFO takes the requests that are to be performed and the status FIFO reports the results. It is possible to get into the situation where there are more free spaces in the command FIFO than the status FIFO if we don't empty the status FIFO quickly enough resulting in a possible overflow of the status FIFO. This can result in incorrect status being reported in the status FIFO. Make sure that when we are submitting requests the number of requests that have been dispatched but not yet popped from the status FIFO does not exceed the size of a single FIFO. Signed-off-by:
Jamie Iles <jamie@jamieiles.com> Signed-off-by:
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Brilly Wu authored
Add new SHA-1/256 module that never needs any fallback and just calls the PadLock hardware instruction supported from VIA Nano processors to implement the "update" and "final" function. They are respectively named "sha1_alg_nano" and "sha256_alg_nano", and will be used on any VIA Nano processor or the later ones. On VIA C7 CPU, the "sha1_alg" and "sha256_alg" modules will still be used as before. Signed-off-by:
Brilly Wu <brillywu@viatech.com.cn> Signed-off-by:
Kary Jin <karyjin@viatech.com.cn> Signed-off-by:
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Kim Phillips authored
- all the integration parameters have been captured by the binding. - the block name really uniquely identifies this hardware. Some advocate putting SoC names everywhere in case software needs to work around some chip-specific bug, but more precise SoC information already exists in SVR, and board information already exists in the top-level device tree node. Note that sometimes the SoC name is a worse identifier than the block version, as the block version can change between revisions of the same SoC. As a matter of historical reference, neither SEC versions 2.x nor 3.x (driven by talitos) ever needed CHIP references. Signed-off-by:
Grant Likely <grant.likely@secretlab.ca> Signed-off-by:
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Dan Carpenter authored
ARRAY_SIZE() was intended here instead of sizeof(). sizeof() is four times larger than ARRAY_SIZE(). outstr is normally 256 chars so printing garbage to it could overfill the buffer and corrupt memory. Signed-off-by:
Dan Carpenter <error27@gmail.com> Acked-by:
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Dan Carpenter authored
t_alg is an ERR_PTR here so we can't dereference it. Signed-off-by:
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Kim Phillips authored
Help clarify that the number trailing in compatible nomenclature is the version number of the device, i.e., change: "fsl,p4080-sec4.0", "fsl,sec4.0"; to: "fsl,p4080-sec-v4.0", "fsl,sec-v4.0"; Signed-off-by:
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Kim Phillips authored
The SEC4 supercedes the SEC2.x/3.x as Freescale's Integrated Security Engine. Its programming model is incompatible with all prior versions of the SEC (talitos). The SEC4 is also known as the Cryptographic Accelerator and Assurance Module (CAAM); this driver is named caam. This initial submission does not include support for Data Path mode operation - AEAD descriptors are submitted via the job ring interface, while the Queue Interface (QI) is enabled for use by others. Only AEAD algorithms are implemented at this time, for use with IPsec. Many thanks to the Freescale STC team for their contributions to this driver. Signed-off-by:
Steve Cornelius <sec@pobox.com> Signed-off-by:
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