- 25 Jul, 2023 4 commits
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Srinivasan Shanmugam authored
Adhere to linux coding style Fixes the following: WARNING: Prefer IS_ENABLED(<FOO>) to CONFIG_<FOO> || CONFIG_<FOO>_MODULE +#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) WARNING: Prefer IS_ENABLED(<FOO>) to CONFIG_<FOO> || CONFIG_<FOO>_MODULE +#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Jonathan Kim authored
MES can concurrently schedule queues on the device that require exclusive device access if marked exclusively_scheduled without the requirement of GWS. Similar to the F32 HWS, MES will manage quality of service for these queues. Use this for cooperative groups since cooperative groups are device occupancy limited. Since some GFX11 devices can only be debugged with partial CUs, do not allow the debugging of cooperative groups on these devices as the CU occupancy limit will change on attach. In addition, zero initialize the MES add queue submission vector for MES initialization tests as we do not want these to be cooperative dispatches. Signed-off-by:
Jonathan Kim <jonathan.kim@amd.com> Reviewed-by:
Felix Kuehling <felix.kuehling@amd.com> Signed-off-by:
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Horace Chen authored
[Why] Current SR-IOV will not set GC to off state, while it is a real GC hard reset. Whthout GFX off flag, driver may do gfxhub invalidation before firmware load and gfxhub gart enable. This operation may cause CP to become busy because GC is not in the right state for invalidation. [How] Add a function for SR-IOV to clean up some sw state before recover. Set adev->gfx.is_poweron to false to prevent gfxhub invalidation before gfx firmware autoload complete. Signed-off-by:
Horace Chen <horace.chen@amd.com> Reviewed-by:
HaiJun Chang <HaiJun.Chang@amd.com> Signed-off-by:
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Jane Jian authored
Report current GFX clock also from average clock value as the original CurrClock data is not valid/accurate any more as per FW team Signed-off-by:
Jane Jian <Jane.Jian@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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- 21 Jul, 2023 10 commits
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Yang Li authored
Use colon to separate parameter name from their specific meaning. silence the warning: drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c:793: warning: Function parameter or member 'adev' not described in 'amdgpu_vm_pte_update_noretry_flags' Reviewed-by:
Randy Dunlap <rdunlap@infradead.org> Signed-off-by:
Yang Li <yang.lee@linux.alibaba.com> Signed-off-by:
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Mario Limonciello authored
If the second call to amdgpu_bo_create_kernel() fails, the memory allocated from the first call should be cleared. If the third call fails, the memory from the second call should be cleared. Fixes: b95b5391 ("drm/amdgpu/psp: move PSP memory alloc from hw_init to sw_init") Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Reviewed-by:
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Victor Lu authored
An instance of for_each_inst() was not changed to match its new behaviour and is causing a loop. v2: remove tmp_mask variable Fixes: b579ea63 ("drm/amdgpu: Modify for_each_inst macro") Signed-off-by:
Victor Lu <victorchengchi.lu@amd.com> Acked-by:
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Lijo Lazar authored
XCP_CTL register is expected to be programmed by firmware. Under certain conditions FW may not have programmed it correctly. As a workaround, program it when FW has not programmed the right values. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Jonathan Kim authored
Update the list of devices that require the cwsr trap handling workaround for debugging use cases. Signed-off-by:
Ruili Ji <ruili.ji@amd.com> Reviewed-by:
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Samuel Holland authored
clang on RISC-V appears to be unaffected by the bug causing excessive stack usage in calculate_bandwidth(). clang 16 with -fstack-usage reports a 304 byte stack frame size with CONFIG_ARCH_RV32I, and 512 bytes with CONFIG_ARCH_RV64I. Reviewed-by:
Nathan Chancellor <nathan@kernel.org> Tested-by:
Samuel Holland <samuel.holland@sifive.com> Signed-off-by:
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Aurabindo Pillai authored
[Why&How] Internal subvp state is not referenced in driver code, so it can be removed. Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Srinivasan Shanmugam authored
Fixes the following checkpatch.pl: WARNING: printk() should include KERN_<LEVEL> facility level Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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sguttula authored
This patch will enable secure decode playback on VCN4_0_2 Signed-off-by:
sguttula <Suresh.Guttula@amd.com> Reviewed-by:
Leo Liu <leo.liiu@amd.com> Signed-off-by:
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Mario Limonciello authored
The VBIOS part number is read both in amdgpu_atom_parse() as well as in atom_get_vbios_pn() and stored twice in the `struct atom_context` structure. Remove the first unnecessary read and move the `pr_info` line from that read into the second. v2: squash in unused variable removal Signed-off-by:
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- 18 Jul, 2023 26 commits
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Guchun Chen authored
~0 as no xcp partition is used in several places, so improve its definition by a macro for code consistency. Suggested-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Guchun Chen authored
Other PDs/PTs allocation should just use the same xcp_id as that stored in root PD. Suggested-by:
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Guchun Chen authored
Recent code set xcp_id stored from file private data when opening device to amdgpu bo for accounting memory usage etc, but not all VMs are attached to this fpriv structure like the vm cases in amdgpu_mes_self_test, otherwise, KASAN will complain below out of bound access. And more importantly, VM code should not touch fpriv structure, so drop fpriv code handling from amdgpu_vm_pt. [ 77.292314] BUG: KASAN: slab-out-of-bounds in amdgpu_vm_pt_create+0x17e/0x4b0 [amdgpu] [ 77.293845] Read of size 4 at addr ffff888102c48a48 by task modprobe/1069 [ 77.294146] Call Trace: [ 77.294178] <TASK> [ 77.294208] dump_stack_lvl+0x49/0x63 [ 77.294260] print_report+0x16f/0x4a6 [ 77.294307] ? amdgpu_vm_pt_create+0x17e/0x4b0 [amdgpu] [ 77.295979] ? kasan_complete_mode_report_info+0x3c/0x200 [ 77.296057] ? amdgpu_vm_pt_create+0x17e/0x4b0 [amdgpu] [ 77.297556] kasan_report+0xb4/0x130 [ 77.297609] ? amdgpu_vm_pt_create+0x17e/0x4b0 [amdgpu] [ 77.299202] __asan_load4+0x6f/0x90 [ 77.299272] amdgpu_vm_pt_create+0x17e/0x4b0 [amdgpu] [ 77.300796] ? amdgpu_init+0x6e/0x1000 [amdgpu] [ 77.302222] ? amdgpu_vm_pt_clear+0x750/0x750 [amdgpu] [ 77.303721] ? preempt_count_sub+0x18/0xc0 [ 77.303786] amdgpu_vm_init+0x39e/0x870 [amdgpu] [ 77.305186] ? amdgpu_vm_wait_idle+0x90/0x90 [amdgpu] [ 77.306683] ? kasan_set_track+0x25/0x30 [ 77.306737] ? kasan_save_alloc_info+0x1b/0x30 [ 77.306795] ? __kasan_kmalloc+0x87/0xa0 [ 77.306852] amdgpu_mes_self_test+0x169/0x620 [amdgpu] v2: without specifying xcp partition for PD/PT bo, the xcp id is -1. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2686 Fixes: 3ebfd221 ("drm/amdkfd: Store xcp partition id to amdgpu bo") Signed-off-by:
Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com> Reviewed-by:
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Guchun Chen authored
file_priv needs to be setup firstly, otherwise, root PD will always be allocated on partition 0, even if opening the device from other partitions. Fixes: 3ebfd221 ("drm/amdkfd: Store xcp partition id to amdgpu bo") Signed-off-by:
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Victor Lu authored
Add RLCG interface support for gfx v9.4.3 and multiple XCCs. Do not enable it yet. v2: Fix amdgpu_rlcg_reg_access_ctrl init, add support for multiple XCCs in amdgpu_mm_wreg_mmio_rlc v3: Use GET_INST() when indexing amdgpu_rlcg_reg_access_ctrl Signed-off-by:Zhigang Luo <zhigang.luo@amd.com> Signed-off-by:
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Aric Cyr authored
This version brings along following fixes: - Update 128b/132b downspread factor to 0.3% - Add helpers to get DMUB FW boot options - Initialize necessary uninitialized variables - Add stream overhead in BW calculations for 128b/132b - Add link encoding to timing BW calculation parameters - Prevent vtotal from being set to 0 - Fix race condition when turning off an output alone - Keep PHY active for DP displays on DCN31 - Fix ASIC check in aux timeout workaround - ABM pause toggle - Add missing triggers for full updates - Disable MPC split by default on special asic - Add additional refresh rate conditions for SubVP cases - Fix DP2 link training failure with RCO - Reenable all root clock gating options - Cache backlight_millinits in link structure and setting brightness accordingly - Refine to decide the verified link setting - Update SW cursor fallback for subvp high refresh Acked-by:
Alan Liu <haoping.liu@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Alvin Lee authored
[Description] - Full update was missed for the following cases: - Idle optimization is enabled - Plane is not in current context - Also don't clear surface updates at end of commit_plane_for_stream_fast as they are cleared at the beginning of each flip (only stream updates need to be cleared in case there is no stream update in the next flip) Reviewed-by:
Samson Tam <samson.tam@amd.com> Acked-by:
Alvin Lee <alvin.lee2@amd.com> Tested-by:
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Reza Amini authored
[why] Allow ABM states to be transferred across display adapters for smooth display transitions. [how] We call DMUB to pause and get ABM states. We transfer data to other gpu, and deliver data and ask ABM to un-pause. Reviewed-by:
Harry Vanzylldejong <harry.vanzylldejong@amd.com> Acked-by:
Reza Amini <reza.amini@amd.com> Tested-by:
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Taimur Hassan authored
[Why] Aux write was meant to be ASIC specific, and is causing compliance failures on newer parts. [How] Make workaround specific to single ASIC. Reviewed-by:
Michael Strauss <michael.strauss@amd.com> Acked-by:
Taimur Hassan <syed.hassan@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[Why & How] Port of a change that went into DCN314 to keep the PHY enabled when we have a connected and active DP display. The PHY can hang if PHY refclk is disabled inadvertently. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
Josip Pavic <josip.pavic@amd.com> Acked-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by:
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Daniel Miess authored
[Why] In dcn314 DML the destination pipe vtotal was being set to the crtc adjustment vtotal_min value even in cases where that value is 0. [How] Only set vtotal to the crtc adjustment vtotal_min value in cases where the value is non-zero. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
Daniel Miess <daniel.miess@amd.com> Tested-by:
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George Shen authored
[Why] There certain cases where the timing BW is dependent on the type of link encoding in use. Thus to calculate the correct BW required for a given timing, the link encoding should be added as a parameter. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
George Shen <george.shen@amd.com> Tested-by:
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George Shen authored
[Why] Current BW calculations do not account for the additional padding added for uncompressed pixel-to-symbol packing. This results in X.Y being too low for 128b/132b SST streams in certain scenarios. If X.Y is too low, end user can observe image corruption. [How] Add function to calculate stream overhead to timing BW calculation for 128b/132b SST cases. Reviewed-by:
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Meera Patel authored
This commit initializes uninitialized variables. For some compilers uninitialized variable warnings are treated as Error. Reviewed-by:
Meera Patel <meera.patel@amd.com> Tested-by:
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Cruise Hung authored
[Why & How] To query the bits and print them out for debug purposes. Reviewed-by:
Cruise Hung <cruise.hung@amd.com> Tested-by:
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Aric Cyr authored
This version brings along following fixes: - Setup stream encoder before link enable for TMDS - Use is_dig_enable function instead of dcn10 hardcode - Re-add aux intercept disable delay generically for 2+ LTTPRs - Add polling method to handle MST reply packet - Remove unused function - Improve the include of header file - Add missing static - Hardcode vco_freq for dcn316 - Reduce stack size - Skip enabling DMCUB when using emulation - Check TG is non-null before checking if enabled - Update scaler recout data for visual confirm - Skip querying caps when DMCUB emulation is in use Acked-by:
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Zhikai Zhai authored
[WHY] All of pipes will be used when the MPC split enable on the dcn which just has 2 pipes. Then MPO enter will trigger the minimal transition which need programe dcn from 2 pipes MPC split to 2 pipes MPO. This action will cause lag if happen frequently. [HOW] Disable the MPC split for the platform which dcn resource is limited Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
Zhikai Zhai <zhikai.zhai@amd.com> Tested-by:
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George Shen authored
[Why] Updating downspread factor to 0.3% to add additional margin to account for potential link rate deviations (up to 300ppm as per the DP spec). Reviewed-by:
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Alan Liu authored
[Why] When 2 threads are doing commit_tail parallelly, one thread could commit new streams to dc state but another thread remove it from dc right away. [How] If we don't have new dm state change from commit_check, then we should not call dc_commit_streams() in commit_tail. A new function amdgpu_dm_commit_streams() is introduced to refator dc_commit_stream() adjacent code and fix this issue. Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Acked-by:
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Samson Tam authored
[Why] Want to further constrain these refresh rate conditions for SubVP: - SubVP + SubVP: either both <= 120Hz or both between 120-165Hz - SubVP + DRR: SubVP <= 120Hz - SubVP + VBlank: SubVP <= 120Hz [How] Add constraints in subvp_subvp_admissable(), dcn32_subvp_drr_admissable() and dcn32_subvp_vblank_admissable() Reviewed-by:
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Zhikai Zhai authored
[WHY] We return false by default when link training fail at link loss. It will cause we get a fail verified link caps directly. [HOW] Record the highest verified link caps. Use the recorded value as the verified link caps if it is not successful in the last attempt to avoid to use the lowest link setting. Reviewed-by:
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Daniel Miess authored
[Why] When RCO is enabled for symclk32_le we get failures during DP2 link traing compliance tests. [How] Break out symclk32_le RCO into a separate function that is called for hpo when link is enabled/disabled. Reviewed-by:
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Nicholas Susanto authored
[Why] Need to save the cached backlight level so that display lights up using appropriate brightness level instead of the default brightness when waking up from s0i3. [How] Adding a backlight level cache in link structure. Also instead on calling set_default_brightness_aux, check if cached values exists. Reviewed-by:
Nicholas Susanto <nicholas.susanto@amd.com> Tested-by:
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Daniel Miess authored
[Why & How] Re-enable all RCO options now that all known issues with RCO have been addressed Reviewed-by:
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Alvin Lee authored
[Description] Since SubVP high refresh is now enabled, we must fallback to SW cursor under if we're in a SubVP high refresh config Reviewed-by:
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Nicholas Kazlauskas authored
[Why] Workaround to avoid accessing DMCUB state too early if the emulator is in use - we don't support any of the features the caps are querying with emulation anyway. [How] Guard the query if emulation is in use. Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Acked-by:
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