- 05 Jun, 2024 40 commits
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Jesse Zhang authored
kfd_create_vcrat_image_gpu itself checks the avail_size at the start. So the value of avail_size is at least VCRAT_SIZE_FOR_GPU(16384), minus struct crat_header(40UL) and struct crat_subtype_compute(40UL) it cannot be less than 0. Signed-off-by:
Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by:
Felix Kuehling <felix.kuehling@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Jesse Zhang authored
The expression caps | HSA_CAP_TRAP_DEBUG_PRECISE_MEMORY_OPERATIONS_SUPPORTED and caps | HSA_CAP_TRAP_DEBUG_PRECISE_ALU_OPERATIONS_SUPPORTED are always 1/true regardless of the values of its operand. Fixes: 9243240b ("drm/amdkfd: enable single alu ops for gfx12") Signed-off-by:
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Jesse Zhang authored
To fix the warning about unused value, remove the use_static and use the parameter is_static directly. Signed-off-by:
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Alvin Lee authored
[Description] Refactor code and move fpo_in_use into stream_status to avoid unexpected changes to previous dc_state (i.e., current_state). Since stream pointers are shared between current and new dc_states, updating parameters of one stream will update the other as well which causes unexpected behaviors (i.e., checking that fpo_in_use isn't set in previous state and set in the new state is invalid). To avoid incorrect updates to current_state, move the fpo_in_use flag into dc_stream_status since stream_status is owned by dc and are not shared between different dc_states. Reviewed-by:
Samson Tam <samson.tam@amd.com> Acked-by:
Zaeem Mohamed <zaeem.mohamed@amd.com> Signed-off-by:
Alvin Lee <alvin.lee2@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Alvin Lee authored
[Description] Today for MED update type we do not call update clocks. However, for FPO the assumption is that update clocks should be called to disable P-State switch before any HW programming since FPO in FW and driver are not synchronized. This causes an issue where on a MED update, an FPO P-State switch could be taking place, then driver forces P-State disallow in the below code and prevents FPO from completing the sequence. In this case we add a check to avoid re-programming (and thus re-setting) the P-State force register by only reprogramming if the pipe was not previously Subvp or FPO. The assumption is that the P-State force register should be programmed correctly the first time SubVP / FPO was enabled, so there's no need to update / reset it if the pipe config has never exited SubVP / FPO. Reviewed-by:
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Joan Lee authored
[why & how] Sometimes read DPCD return fail while result not retrieved yet. Add retries mechanism in Replay handle hpd irq to get real result. Reviewed-by:
Jerry Zuo <jerry.zuo@amd.com> Acked-by:
Joan Lee <joan.lee@amd.com> Tested-by:
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Nicholas Susanto authored
[Why] When an eDP with high clock states is going into s0i3, stream_count is 0. This causes DML to not update the clks to the lowest state and blocking us to enter s0i3 since eDP is out of vmin. [How] When stream_count is 0, set all the clocks to the lowest state. Reviewed-by:
Jun Lei <jun.lei@amd.com> Acked-by:
Nicholas Susanto <nicholas.susanto@amd.com> Tested-by:
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Jay Cornwall authored
A wavefront may deallocate its VGPRs at the end of a program while waiting for memory transactions to complete. If it subsequently receives a context save exception it will be unable to save, since this requires VGPRs. In this case the trap handler should terminate the wavefront. Fixes intermittent VM faults under context switching load. V2: Use S_ENDPGM instead of S_ENDPGM_SAVED for performance counters Signed-off-by:
Jay Cornwall <jay.cornwall@amd.com> Reviewed-by:
Lancelot Six <lancelot.six@amd.com> Signed-off-by:
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Chris Park authored
[Why] Page table definition increased up to 2MB. [How] Define new use case of page table for VA. Reviewed-by:
Chris Park <chris.park@amd.com> Tested-by:
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Joshua Aberback authored
[Why] Currently there's an issue on DCN401 that prevents oled eDP panels from being lit up that is still under investigation. To unblock dev work while investigating, we can work around the issue by skipping toggling the enablement of the backlight. [How] - new debug bit that will skip touching backlight enable DPCD for oled Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
Joshua Aberback <joshua.aberback@amd.com> Tested-by:
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Chun-LiangChang authored
[Why] Add parameters for set_abm_event to enable varibright scaling. VariBright Scaling is a feature to refer to system states like 1. Power mode 2. Battery Life percent 3. FullScreen video 4. Backlight slider to adjust variBright strength to get low power or user experience. [How] Add parameters of set_abm_event for VB Scaling Reviewed-by:
Chun-LiangChang <chuchang@amd.com> Tested-by:
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Joshua Aberback authored
[Why] The values calculated in optc1_get_otg_active_size are assigned to the wrong output parameters, vertical blank is being used for horizontal size and vice versa. This results in DPG test pattern looking wrong during hardware init, as the DPG dimensions get assigned from this output, and potentially other issues. Reviewed-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
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Dillon Varone authored
[WHY&HOW] When updating clocks via SMU, DAL needs to wait for requests to be fulfilled before proceeding. Reviewed-by:
Dillon Varone <dillon.varone@amd.com> Tested-by:
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Wenjing Liu authored
[why] In order to support glitchless display clock ramping for virtual stream, we must turn on symclk for stream encoder. The code will power on phy and enable symclk for dio encoder during virtual stream dpms sequence. Reviewed-by:
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yi-lchen authored
[why] Vbios & Driver have difference pixel rate div policy. When enabling fast boot & performing blank & unblank w/o timing setting, pixel clock & pixel rate dividor are not match. It would cause too high pixel reate and eDP would be black screen. [How] We would keep pixel rate div setting by Vbios until next timing setting. Reviewed-by:
yi-lchen <yi-lchen@amd.com> Tested-by:
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Alex Deucher authored
This reverts commit 6670142d. Pierre-Eric reported problems with this on his navi33. Revert for now until we understand what is going wrong. Acked-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Signed-off-by:
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Alex Deucher authored
Add some additional registers. Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Marek Olšák authored
define new gfx12 uapi flags Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Acked-by:
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Jesse Zhang authored
The varible uncached set false, the condition uncached cannot be true. So remove the dead code, mapping flags will set the flag AMDGPU_VM_MTYPE_UC in else. Signed-off-by:
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Shane Xiao authored
This patch changes the implementation of AMDGPU_PTE_MTYPE_NV10, clear the bits before setting the new one. Suggested-by:
longlyao <Longlong.Yao@amd.com> Signed-off-by:
Shane Xiao <shane.xiao@amd.com> Reviewed-by:
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Yifan Zhang authored
This patch to disable lane0 L1TLB and enable lane1 L1TLB. Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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Yifan Zhang authored
This patch to configure mmhub3.3 SAW registers Signed-off-by:
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Tasos Sahanidis authored
Flexible arrays used [1] instead of []. Replace the former with the latter to resolve multiple UBSAN warnings observed on boot with a BONAIRE card. In addition, use the __counted_by attribute where possible to hint the length of the arrays to the compiler and any sanitizers. Signed-off-by:
Tasos Sahanidis <tasos@tasossah.com> Signed-off-by:
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Colin Ian King authored
There are a few spelling mistakes in dml2_printf messages. Fix them. Reviewed-by:
Randy Dunlap <rdunlap@infradead.org> Signed-off-by:
Colin Ian King <colin.i.king@gmail.com> Signed-off-by:
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Sunil Khatri authored
Fix comments and error messages to rightly represent the information. Reviewed-by:
Sunil Khatri <sunil.khatri@amd.com> Signed-off-by:
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Sunil Khatri authored
Rename the variable ip_dump_cp_queues to ip_dump_compute_queue as it represent compute queues. Reviewed-by:
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Sunil Khatri authored
Add gfx9 support of CP queue registers for all queues to be used by devcoredump. Reviewed-by:
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Sunil Khatri authored
Add support of gfx9 ipdump print so devcoredump could trigger it to dump the captured registers in devcoredump. Signed-off-by:
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Sunil Khatri authored
Add general registers of gfx9 in ipdump for devcoredump support. Signed-off-by:
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Srinivasan Shanmugam authored
This commit fixes a type mismatch in the amdgpu_gfx_kiq_init_ring function triggered by the snprintf function expecting unsigned char arguments due to the '%hhu' format specifier, but receiving int and u32 arguments. The issue occurred because the arguments xcc_id, ring->me, ring->pipe, and ring->queue were of type int and u32, not unsigned char. This led to a type mismatch when these arguments were passed to snprintf. To resolve this, the snprintf line was modified to cast these arguments to unsigned char. This ensures that the arguments are of the correct type for the '%hhu' format specifier and resolves the warning. Fixes the below: >> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:333:4: warning: format >> specifies type 'unsigned char' but the argument has type 'int' >> [-Wformat] xcc_id, ring->me, ring->pipe, ring->queue); ^~~~~~ >> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:333:12: warning: format >> specifies type 'unsigned char' but the argument has type 'u32' (aka >> 'unsigned int') [-Wformat] xcc_id, ring->me, ring->pipe, ring->queue); ^~~~~~~~ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:333:22: warning: format specifies type 'unsigned char' but the argument has type 'u32' (aka 'unsigned int') [-Wformat] xcc_id, ring->me, ring->pipe, ring->queue); ^~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c:333:34: warning: format specifies type 'unsigned char' but the argument has type 'u32' (aka 'unsigned int') [-Wformat] xcc_id, ring->me, ring->pipe, ring->queue); ^~~~~~~~~~~ 4 warnings generated. Fixes: 0ea55445 ("drm/amdgpu: Fix snprintf usage in amdgpu_gfx_kiq_init_ring") Reported-by:kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202405250446.XeaWe66u-lkp@intel.com/ Cc: Lijo Lazar <lijo.lazar@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Acked-by:
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Jesse Zhang authored
Potentially overflowing expression mall_size_per_umc * adev->gmc.num_umc with type unsigned int (32 bits, unsigned) is evaluated using 32-bit arithmetic,and then used in a context that expects an expression of type u64 (64 bits, unsigned). Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Hawking Zhang authored
AMDGPU_RAS_GPU_ERR_BOOT_STATUS field is no longer valid. The polling sequence is also simplifed according to the latest firmware change. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Bill Wendling authored
Work for __counted_by on generic pointers in structures (not just flexible array members) has started landing in Clang 19 (current tip of tree). During the development of this feature, a restriction was added to __counted_by to prevent the flexible array member's element type from including a flexible array member itself such as: struct foo { int count; char buf[]; }; struct bar { int count; struct foo data[] __counted_by(count); }; because the size of data cannot be calculated with the standard array size formula: sizeof(struct foo) * count This restriction was downgraded to a warning but due to CONFIG_WERROR, it can still break the build. The application of __counted_by on the states member of 'struct _StateArray' triggers this restriction, resulting in: drivers/gpu/drm/radeon/pptable.h:442:5: error: 'counted_by' should not be applied to an array with element of unknown size because 'ATOM_PPLIB_STATE_V2' (aka 'struct _ATOM_PPLIB_STATE_V2') is a struct type with a flexible array member. This will be an error in a future compiler version [-Werror,-Wbounds-safety-counted-by-elt-type-unknown-size] 442 | ATOM_PPLIB_STATE_V2 states[] __counted_by(ucNumEntries); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1 error generated. Remove this use of __counted_by to fix the warning/error. However, rather than remove it altogether, leave it commented, as it may be possible to support this in future compiler releases. Cc: stable@vger.kernel.org Closes: https://github.com/ClangBuiltLinux/linux/issues/2028 Fixes: efade6fe ("drm/radeon: silence UBSAN warning (v3)") Signed-off-by:Bill Wendling <morbo@google.com> Co-developed-by:
Nathan Chancellor <nathan@kernel.org> Signed-off-by:
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Alex Deucher authored
This fixes HDP flushes on systems with non-4K pages. Reviewed-by:
Yang Wang <kevinyang.wang@amd.com> Signed-off-by:
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Tvrtko Ursulin authored
Currently when one enables driver debugging dmesg gets spammed, at I suspect vblank rate, with messages like: [drm:amdgpu_dm_atomic_check [amdgpu]] MPO enablement requested on crtc:[00000000f073c3bb] Fix if by converting some logging from deprecated and incorrect DRM_DEBUG_DRIVER to drm_dbg_atomic. Plus some localized drive-by changes to drm_dbg_kms. By no means an exhaustive conversion but at least it allows turning on driver debug selectively. Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Hawking Zhang authored
Add estimate of how much vram we need to reserve for RAS when caculating the total available vram. v2: apply the change to MP0 v13_0_2 and v13_0_14 Signed-off-by:
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Tao Zhou authored
And also make sure the value of msg[1].len should be in the range of u16. Signed-off-by:
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Jay Cornwall authored
Fix LDS size interpretation: 512 bytes (>= gfx12) vs 256 (< gfx12). Ensure STATE_PRIV.BARRIER_COMPLETE cannot change after reading or before writing. Other waves in the threadgroup may cause this field to assert if they complete the barrier. Do not overwrite EXCP_FLAG_PRIV.{SAVE_CONTEXT,HOST_TRAP} when restoring this register. Both of these fields can assert while the wavefront is running the trap handler. Signed-off-by: -
David (Ming Qiang) Wu authored
We have messages when the VCN fails to initialize and there is no need to report on success. Also PSP loading FWs is the default for production. Acked-by:
Sonny Jiang <sonjiang@amd.com> Signed-off-by:
David (Ming Qiang) Wu <David.Wu3@amd.com> Signed-off-by:
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Shane Xiao authored
This patch changes the implementation of AMDGPU_PTE_MTYPE_GFX12, clear the bits before setting the new one. This fixed the potential issue that GFX12 setting memory to NC. v2: Clear mtype field before setting the new one (Alex) v3: Fix typo (Felix) Suggested-by:
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