1. 25 Feb, 2002 6 commits
    • Russell King's avatar
      EPXA10DB/Camelot ARM machine updates. · b7783fa9
      Russell King authored
      b7783fa9
    • Russell King's avatar
      Rationalise interrupt handling on ARM. With the old code, we had · 3991853c
      Russell King authored
      loops within loops within loops checking until each IRQ level didn't
      have any more interrupts for us.  This caused both latency problems,
      and locked out any chance of handling a second interrupt from down
      the chain while one on that chain was already in progress.
      
      The new structure splits out the machine specific IRQ handlers from
      the Linux driver specific IRQ handlers, giving the machine specific
      handlers much greater flexibility in handling the interrupt.  We
      also suck the SA1100 IRQ edge selection function into the IRQ core.
      3991853c
    • Russell King's avatar
      1ea95bdc
    • Russell King's avatar
      ARM preempt and scheduler fixups for 2.5.5 · ba1074cf
      Russell King authored
      ba1074cf
    • Russell King's avatar
      Fix nwfpe so GDB can debug user space floating point again. · ad889c6b
      Russell King authored
      Patch 960/1 (Peter Teichmann):
         NWFPE patch to be more compliant to IEEE-754
      
      1. The RND/URD instruction was handled as int_to_float(float_to_int
         (number)) which is wrong because it only works for floating point
         numbers that fit in an integer.
      
      2. The FLT instruction was setting the rounding precision for
         extended precision calculations, which is not necessary
         (probably a historic relict) but has undesirable side effects
         on all extended precision calculations.
      ad889c6b
    • Russell King's avatar
      Clean up ARM TLB handling code; previously there was a lot of code · a6560a26
      Russell King authored
      replication across each processor type, each handling alignment of
      addresses slightly differently.  We unify this mess, and allow for
      greater flexibility in the per-CPU architecture TLB handlers.
      
      We also start to remove the ARM cache.h -> cpu_*.h -> proc-fns.h mess
      making the code cleaner and easier to follow.
      
      Documentation describing the expected behaviour of each TLB function
      for the 32-bit ARM processors is also included.
      a6560a26
  2. 21 Feb, 2002 19 commits
  3. 20 Feb, 2002 15 commits