- 15 May, 2024 4 commits
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Jouni Högander authored
We are about to reuse psr2_enabled for panel replay as well. Rename it as sel_update_enabled to avoid confusion. v3: Rebase v2: Rebase Signed-off-by:
Jouni Högander <jouni.hogander@intel.com> Reviewed-by:
Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-5-jouni.hogander@intel.com
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Jouni Högander authored
We are about to enable Panel Replay Selective update mode. Vsc revision 0x6 for Panel Replay no matter if it is selective update or full frame update mode. Take this into account when preparing VSC SDP package. Signed-off-by:
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Jouni Högander authored
After setting has_psr for panel replay as well crtc state dump is improperly printing "psr: enabled" for Panel Replay as well. Fix this by checking also has_panel_replay. Fixes: 5afa6e49 ("drm/i915/psr: Set intel_crtc_state->has_psr on panel replay as well") Signed-off-by:
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Jouni Högander authored
We are going to reuse has_psr2 for panel_replay as well. Rename it as has_sel_update to avoid confusion. v3: do not add has_psr check into psr2 case in intel_dp_compute_vsc_sdp v2: Rebase Signed-off-by:
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- 14 May, 2024 1 commit
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Luca Coelho authored
The function descriptions are optional and have not yet been added to the DMC wakelock code, so we shouldn't try to use it. Since this is a regression, remove the kernel-doc entry for DMC wakelocks for now. The proper documentation will be added in a future patch. Fixes: 765425f5 ("drm/i915/display: add support for DMC wakelocks") Signed-off-by:
Luca Coelho <luciano.coelho@intel.com> Reviewed-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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- 13 May, 2024 14 commits
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Jani Nikula authored
Nothing in xe needs xe->sb_lock. None of the i915 display code using ->sb_lock gets built with xe, and in any case that would be wrong as xe uses gt->pcode.lock for this. Acked-by:
Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by:
Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240510094313.3422982-2-jani.nikula@intel.comSigned-off-by:
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Jani Nikula authored
The xe->enabled_irq_mask member has never been used for anything. Acked-by:
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Ville Syrjälä authored
Rename the fb pinning functions such that their name directly informs us what gets pinned into which address space. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240506125718.26001-10-ville.syrjala@linux.intel.comReviewed-by:
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Ville Syrjälä authored
We use a mix of 'intel_fb' vs. 'ifbdev->fb' in the same function. Both should be pointing at the same thing. Make things less confusing by just getting existing fb from 'ifbdev->fb' at the start and then sticking with the local 'fb' (renamed from the 'intel_fb') until the very end. v2: rebase Signed-off-by:
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Ville Syrjälä authored
Change intel_fbdev_fb_alloc() to return struct intel_fb instead of struct drm_framebuffer. Let's us eliminate some annoying aliasing variables in the fbdev setup code. v2: Assing the results to the correct variable (Jani) Fix xe's copy Signed-off-by: -
Ville Syrjälä authored
Make the 'fb' pointers const in the pinning code. We never want to mutate these. Also nuke a few aliasing fb vs. intel_fb cases by just using the more specific type everywhere in the same function. Signed-off-by:
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Uma Shankar authored
WA_14020863754: Corner case with Min Hblank Fix can cause audio hang Issue: Previously a fix was made to avoid issues with extremely small hblanks, called the "Min Hblank Fix". However, this can potentially cause an audio hang. Workaround : During "Audio Programming Sequence" Audio Enabling - When DP mode is enabled Set mmio offset 0x65F1C bit 18 = 1b, before step #1 "Enable audio Presence Detect" During "Audio Programming Sequence" Audio Disabling - When DP mode is enabled Clear mmio offset 0x65F1C bit 18 = 0b, after step #6 "Disable Audio PD (Presence Detect)" If not clearing PD bit, must also not clear 0x65F1C bit 18 (leave = 1b) v2: Update the platform checks (Jani Nikula) v3: Limited the WA to LNL and BMG, added a helper (Matt Roper) v4: Updated the bit naming, fixed redundant if statement Signed-off-by:
Uma Shankar <uma.shankar@intel.com> Reviewed-by:
Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240509053508.2807834-1-uma.shankar@intel.com
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Suraj Kandpal authored
Write panel override luminance values which helps the TCON decide if tone mapping needs to be enabled or not. Signed-off-by:
Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by:
Sebastian Wick <sebastian.wick@redhat.com> Signed-off-by:
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Suraj Kandpal authored
As of now whenerver HDR is switched on we use the PWM to change the backlight as opposed to AUX based backlight changes in terms of nits. This patch writes to the appropriate DPCD registers to enable aux based backlight using values in nits. --v2 -Fix max_cll and max_fall assignment [Jani] -Fix the size sent in drm_dpcd_write [Jani] --v3 -Content Luminance needs to be sent only for pre-ICL after that it is directly picked up from hdr metadata [Ville] --v4 -Add checks for HDR TCON cap bits [Ville] -Check eotf of hdr_output_data and sets bits base of that value. --v5 -Fix capability check bits. -Check colorspace before setting BT2020 --v6 -Use intel_dp_has_gamut_dip to check if we have capability to send sdp [Ville] -Seprate filling of all hdr tcon related bits into it's own function. -Check eotf data to make sure we are in HDR mode [Sebastian] --v7 -Fix confusion function name for hdr mode check [Jani] -Fix the condition which tells us if we are in HDR mode or not [Sebastian] --v8 -Call fill_hdr_tcon_param unconditionally as some parameters may not be dependent on the fact if we are in hdr mode or not [Sebastian] -Fix some conditions after change in hdr mode check [Sebastian] Signed-off-by:
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Suraj Kandpal authored
Drop comments for EDP HDR DPCD registers as the code and conditions will tell us what can be written where. --v2 -Drop the comments altogether instead of just renaming them [Sebastian] Signed-off-by:
Arun R Murthy <arun.r.murthy@intel.com> Signed-off-by:
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Suraj Kandpal authored
Change INTEL_EDP_HDR_TCON_SDP_COLORIMETRY enable to INTEL_EDP_HDR_TCON_SDP_OVERRIDE_AUX as this bit tells TCON to ignore DPCD colorimetry values and take the one's sent through SDP. --v2 -Fix typo in commit message [Arun] Signed-off-by:
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Suraj Kandpal authored
Add checks to see the HDR capability of TCON panel. Signed-off-by:
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Suraj Kandpal authored
Rename intel to intel cap which is present inside panel.edp struct to make it more sensible to tell us what it contains. Signed-off-by:
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Suraj Kandpal authored
Make has_gamut_metadata_dip() non static so it can also be used to at other places eg in intel_dp_aux_backlight. So that we can check if HW is capable of sending SDP which helps us decide if we use AUX based HDR control or via SDP. --v2 -State reason the function is needed [Arun] Signed-off-by:
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- 10 May, 2024 16 commits
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Ville Syrjälä authored
Be a bit more consistent in our use of integer types in the fb related calculatiosn. u32 we generally only use for ggtt offsets and such, and everything else can be regular (unsigned) ints. There's also an overabundance of consts for local variables in skl_check_main_surface() which is not something we generally do. So get rid of those while at it. Signed-off-by:
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Ville Syrjälä authored
Pull the "does this plane need a physical address?" check into a small helper. Signed-off-by:
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Ville Syrjälä authored
Fence regions are only relevant for GGTT, not DPT. Drop the pointless 'uses_fence' argument from intel_pin_fb_obj_dpt(). Signed-off-by:
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Ville Syrjälä authored
skl_plane_max_stride() is pretty messy. Streamline it and split it into clear skl+ vs. adl+ variants. TODO: Deal with icl and tgl strude limits properly Signed-off-by:
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Ville Syrjälä authored
Plane .max_stride() is already a vfunc so having one made up of two branches based on the display version is silly. Split i9xx_plane_max_stride() into gen2 vs. gen3 variants so that we get rid of said check. Signed-off-by:
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Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_VRR_VSYNC register macro. Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/61b464bedfd75a97ca214e066be5417d790ccb26.1715183162.git.jani.nikula@intel.comSigned-off-by:
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Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_PUSH register macro. Reviewed-by:
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Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_VRR_STATUS2 register macro. Reviewed-by:
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Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_VRR_FLIPLINE register macro. Reviewed-by:
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Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_VRR_VTOTAL_PREV register macro. Reviewed-by:
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Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_VRR_STATUS register macro. Reviewed-by:
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Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_VRR_VMAXSHIFT register macro. Reviewed-by:
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Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_VRR_VMIN register macro. Reviewed-by:
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Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_VRR_VMAX register macro. Reviewed-by:
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Jani Nikula authored
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_VRR_CTL register macro. Reviewed-by:
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Suraj Kandpal authored
Disable HDCP Line Rekeying when HDCP ver > 1.4 and when we are on HDMI TMDS operation for DISPLAY_VER >= 14. --v2 -Wa to be mentioned in comments not in commit message [Jani] -Remove blankline [Jani] --v3 -No need to write what is being done in comments when code is self explanatory [Jani] --v4 -Add comment regarding need of this WA when in TMDS mode [Chaitanya] -Write in chicken register for MTL [CHaitanya] --v5 -Fix comment [Chaitanya] -Use correct set and clear value in intel_de_rmw [Chaitanya] --v6 -No need to define C, D chicken bits it gets calculated [Animesh] Bspec: 49273 Bspec: 69964 Signed-off-by:
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- 09 May, 2024 1 commit
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Ville Syrjälä authored
For some reason xe and i915 each have an identical (fortunately) copy of intel_fbdev_fb.h. The xe copy actually only gets included by xe's intel_fbdev_fb.c, and the i915 copy by everyone else, include intel_fbdev.c which is the actual caller of the functions declared in the header. This means the xe and i915 headers are free to define/declare completely incompatible things and the build would still succeed as long as the symbol names match. That is not a good thing, so let's nuke xe's copy of the header so that everyone will use the same header, and be forced to agree on the same API/ABI. Signed-off-by:
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- 08 May, 2024 4 commits
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Ville Syrjälä authored
Replace the open coded drm_crtc_vblank_crtc() with the real thing. Cc: intel-gfx@lists.freedesktop.org Signed-off-by:
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Ville Syrjälä authored
Define the contents of VBT block 253 (PRD Table). Unfortunately the block has two definitions, with the cutoff supposedly happening on ICL vs. TGL. Also according to some notes it might be that the VBIOS (if that's still a thing) still uses the old definition even on TGL+. Quite the mess. Signed-off-by:
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Ville Syrjälä authored
Declare that VBT block 252 is the "int15 hook". This is some VBIOS only juju so don't bother with a full definition. Signed-off-by:
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Ville Syrjälä authored
Define the contents of the obsolete VBT block 55 (Compression Parameters). This was some early attempt at defining the compression parameters. However the spec says: "This block is obsolete and should not be consumed for any compression programming." Block 56 is the replacement that should actually be used. So let's just name the obsolete old block but not even bother defining the contents. Signed-off-by:
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