- 15 Jul, 2024 5 commits
-
-
Jiaxun Yang authored
Add ip30_defconfig derived from ip27_defconfig to ensure this target is build tested by various kernel testing projects. Signed-off-by:
Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
-
Jiaxun Yang authored
Regenerate defconfig to include some drivers that are used by this platform, including sm712fb, simplefb, rtl8187. Signed-off-by:
-
Jiaxun Yang authored
The LiteX framework provides a convenient and efficient infrastructure to create FPGA Cores/SoCs. We have implemented LiteX support for a couple of opensource MIPS CPU cores including microAptiv UP from MIPS, GS232 from Loongson, and CDIM from CQU. For this platform, devicetree is generated by litex python scripts so there is no devicetree addition necessary. Link: https://github.com/enjoy-digital/litex/pull/1990Signed-off-by:
-
Jiaxun Yang authored
All MIPS64R6 cores so far supports MSA and vz, so it makes sense to enable them in 64R6 default config. Signed-off-by:
-
Jiaxun Yang authored
Fallback march for SB1 should be mips64 instead of mips64r1. Reported-by:
kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202407111851.LwDasTcp-lkp@intel.com/ Fixes: bfc0a330 ("MIPS: Fallback CPU -march flag to ISA level if unsupported") Signed-off-by:
-
- 12 Jul, 2024 10 commits
-
-
Chris Packham authored
Add support for the RTL9302 SoC and the RTL9302C_2xRTL8224_2XGE reference board. The RTL930x family of SoCs are Realtek switches with an embedded MIPS core (800MHz 34Kc). Most of the peripherals are similar to the RTL838x SoC and can make use of many existing drivers. Add in full DSA switch support is still a work in progress. Signed-off-by:
Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by:
-
Chris Packham authored
The bootloader used on the Realtek RTL9302C boards is an ancient vendor fork of U-Boot that doesn't understand device trees. So to run a modern kernel it is necessary use one of the APPENDED_DTB options. When appending the DTB the inintrd information, if present, needs to be inserted into the /chosen device tree node. The bootloader provides the initrd start/size via the firmware environment. Add a fdt fixup that will update the device tree with the initrd information. Signed-off-by:
-
Chris Packham authored
When MACH_REALTEK_RTL is selected automatically select the REALTEK_OTTO_TIMER option in order to support the Realtek platforms that require it. Signed-off-by:
-
Chris Packham authored
Add a compatible string for the interrupt controller found on the rtl930x SoCs. The interrupt controller has registers for VPE1 so these are added as a second reg cell. Signed-off-by:
Rob Herring (Arm) <robh@kernel.org> Signed-off-by:
-
Chris Packham authored
Add the rtl9302 SoC and the Cameo RTL9302C_2xRTL8224_2XGE reference board to the list of Realtek compatible strings. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
-
Chris Packham authored
Add entry for Cameo Communications (https://www.cameo.com.tw/) Signed-off-by:
-
Chris Packham authored
Add device_type = "cpu" to the cpu node for the rtl838x SoC. This resolves the following dtbs_check complaint: cpus: cpu@0: 'cache-level' is a required property Signed-off-by:
Marek Behún <kabel@kernel.org> Signed-off-by:
-
Chris Packham authored
Update the node name for the UARTs to resolve the following dtbs_check complaints: uart@2000: $nodename:0: 'uart@2000' does not match '^serial(@.*)?$' uart@2100: $nodename:0: 'uart@2100' does not match '^serial(@.*)?$' Signed-off-by:
-
Jiaxun Yang authored
Implement ieee754 NAN2008 emulation mode. When this mode is enabled, kernel will accept ELF file compiled for both NaN 2008 and NaN legacy, but if hardware does not have capability to match ELF's NaN mode, __own_fpu will fail for corresponding thread and fpuemu will then kick in. This mode trade performance for correctness, while maintaining support for both NaN mode regardless of hardware capability. It is useful for multilib installation that have both types of binary exist in system. Reviewed-by:
Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by:
-
Hauke Mehrtens authored
This adds code to initialize the USB controller and PHY also on Danube, Amazon SE and AR10. This code is based on the Vendor driver from different UGW versions and compared to the hardware documentation. This patch is included in OpenWrt for many years. Signed-off-by:
Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by:
-
- 09 Jul, 2024 3 commits
-
-
Paul Burton authored
With CM 3.5 the "core-other" register block evolves into the "redirect" register block, which is capable of accessing not only the core local registers of other cores but also the shared/global registers of other clusters. This patch generates accessor functions for shared/global registers accessed via the redirect block, with "redir_" inserted after "gic_" in their names. For example the accessor function: read_gic_config() ...accesses the GIC_CONFIG register of the GIC in the local cluster. With this patch a new function: read_gic_redir_config() ...is added which accesses the GIC_CONFIG register of the GIC in whichever cluster the GCR_CL_REDIRECT register is configured to access. This mirrors the similar redirect block accessors already provided for the CM & CPC. Reviewed-by:
Paul Burton <paulburton@kernel.org> Signed-off-by:
Chao-ying Fu <cfu@wavecomp.com> Signed-off-by:
Dragan Mladjenovic <dragan.mladjenovic@syrmia.com> Signed-off-by:
Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Signed-off-by:
-
Paul Burton authored
This patch introduces a couple of utility functions which help later patches with introducing support for multi-cluster systems. - mips_cps_multicluster_cpus() allows its caller to determine whether the system includes CPUs spread across multiple clusters. This is useful because in some cases behaviour can be more optimal taking this knowledge into account. The means by which we check this is dependent upon the way we probe CPUs & assign their numbers, so keeping this knowledge confined here in arch/mips/ seems appropriate. - mips_cps_first_online_in_cluster() allows its caller to determine whether it is running upon the first CPU online within its cluster. This information is useful in cases where some cluster-wide configuration may need to occur, but should not be repeated if another CPU in the cluster is already online. Similarly to the above this is determined based upon knowledge of CPU numbering so it makes sense to keep that knowledge in arch/mips/. The function is defined in mips-cm.c rather than in asm/mips-cps.h in order to allow us to use asm/cpu-info.h & linux/smp.h without encountering an include nightmare. Signed-off-by:
-
Dominique Martinet authored
This does not matter the least, but there is no other .[ch] file in the repo that is executable, so clean this up. Fixes: 29b83a64 ("MIPS: Octeon: Add PCIe link status check") Signed-off-by:
Dominique Martinet <dominique.martinet@atmark-techno.com> Signed-off-by:
-
- 03 Jul, 2024 9 commits
-
-
Théo Lebrun authored
Register OLB-related files part of the "MOBILEYE MIPS SOCS" MAINTAINERS section. Those include: - drivers (clk-eyeq, reset-eyeq, pinctrl-eyeq5), - dt-bindings (mobileye,eyeq5-olb.yaml file), - bindings includes file <dt-bindings/clock/mobileye,eyeq5-clk.h>. Signed-off-by:
Théo Lebrun <theo.lebrun@bootlin.com> Signed-off-by:
-
Théo Lebrun authored
The OLB ("Other Logic Block") is a system-controller region hosting clock, reset and pin controllers. It contains registers such as I2C speed mode that need to be accessible by other nodes. Remove fixed-clocks previously used; replace references. Add parent crystal clock, fixed at 30MHz. Add pin nodes for all functions. Add mobileye,eyeq5-olb compatible node, hosting clk, reset and pinctrl. Add reset and pinctrl references to UART nodes. Signed-off-by: -
Théo Lebrun authored
Add documentation to describe the "Other Logic Block" system-controller. It deals with three platforms: EyeQ5, EyeQ6L and EyeQ6H. First two have a single instance, whereas EyeQ6H has seven named instances. Features provided are: - Clocks, children to main crystal. Some PLLs and divider clocks. - Resets. Some instances DO NOT have reset. - Pinctrl. Only EyeQ5 has such feature. Those are NOT the only features exposed in OLB system-controllers! Many individual registers, related to IP block integration, can be found. Additional features will be exposed over time. We simplify devicetree phandles to OLB in two ways: - Compatibles exposing a single clock do not ask for a index argument. This means we use EyeQ6H OLB south (it has four clocks): clocks = <&olb_south EQ6HC_SOUTH_PLL_PER>; But use EyeQ6H OLB east (it has one clock): clocks = <&olb_east>; - Compatibles exposing a single reset domain do not ask for a domain index, only a reset index. This means we use EyeQ5 OLB (it has three domains): resets = <&olb 0 10>; But use EyeQ6H west reset (it has one domain): resets = <&olb_west 3>; About pinctrl subnodes: all pins have two functionality, either GPIO or something-else. The latter is pin dependent, we express constraints using many if-then. Reviewed-by: -
Dmitry Torokhov authored
Switch to use software nodes/properties to describe GPIOs for the ADS7846 touchscreen and the SPI controller (away from using GPIO lookup tables). This allows removing use of ADS7846 platform data, which will be going away. Signed-off-by:
Dmitry Torokhov <dmitry.torokhov@gmail.com> Reviewed-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
-
Jiaxun Yang authored
The original sync-r4k did a good job on reducing jitter by determine the "next time value", but it has a limitation that when synchronization being performed too many times due to high core count or CPU hotplug, the timewrap on CPU0 will become unaccpetable. Rework the mechanism based on latest x86 tsc_sync. (It seems like the original implementation is based on tsc_sync at that time, so it's just a refresh.) To improve overall performance. Tesed on Loongson64, Boston, QEMU. Signed-off-by:
-
Jiaxun Yang authored
When we have more than one CPU in system, counter synchronisation overhead can lead to a scenario that sched_clock goes backward when being read from different CPUs. This is accommodated by CONFIG_HAVE_UNSTABLE_SCHED_CLOCK, but it's unavailable on 32bit kernel. We don't want to risk sched_clock correctness, so if we have multiple CPU in system and CONFIG_HAVE_UNSTABLE_SCHED_CLOCK is not set, we just don't use counter as sched_clock source. Signed-off-by:
-
Jiaxun Yang authored
csrc-r4k suffers from SMP synchronization overhead. Select HAVE_UNSTABLE_SCHED_CLOCK to workaround drift between the CPUs on the system. HAVE_UNSTABLE_SCHED_CLOCK requires cmpxchg64, so enable it for 64 bits only. Signed-off-by:
-
Jiaxun Yang authored
CP0 counter suffers from various problems like SMP sync, behaviour on wait. Set CLOCK_SOURCE_MUST_VERIFY and CLOCK_SOURCE_VERIFY_PERCPU, as what x86 did to TSC, to let kernel test it before use. Signed-off-by:
-
Jiaxun Yang authored
Increase frequency addend dividend to 10000000 (10MHz) to reasonably accommodate multi GHz level mips_hpt_frequency. Cap rating of csrc-r4k into 299 to ensure it doesn't go into "Desired" range, given all the drama we have with CP0 count registers (SMP sync, behaviour on wait etc). Signed-off-by:
-
- 27 Jun, 2024 5 commits
-
-
Daniel González Cabanelas authored
The data RAC is left disabled by the bootloader in some SoCs, at least in the core it boots from. Enabling this feature increases the performance up to +30% depending on the task. Signed-off-by:
Daniel González Cabanelas <dgcbueu@gmail.com> Signed-off-by:
Álvaro Fernández Rojas <noltari@gmail.com> [ rework code and reduce code duplication ] Acked-by:
Florian Fainelli <florian.fainelli@broadcom.com> Signed-off-by:
Christian Marangi <ansuelsmth@gmail.com> Signed-off-by:
-
Christian Marangi authored
Add support to provide CBR address from DT to handle broken SoC/Bootloader that doesn't correctly init it. This permits to use the RAC flush even in these condition. To provide a CBR address from DT, the property "brcm,bmips-cbr-reg" needs to be set in the "cpus" node. On DT init, this property presence will be checked and will set the bmips_cbr_addr value accordingly. Also bmips_rac_flush_disable will be set to false as RAC flush can be correctly supported. The CBR address from DT will overwrite the cached one and the one set in the CBR register will be ignored. Also the DT CBR address is validated on being outside DRAM window. Signed-off-by:
-
Christian Marangi authored
Document brcm,bmips-cbr-reg property. Some SoC suffer from a BUG where CBR(Core Base Register) address might be badly or never initialized by the Bootloader or reading it from co-processor registers, if the system boots from secondary CPU, results in invalid address. The CBR address is always the same on the SoC. Usage of this property is to give an address also in these broken configuration/bootloader. Signed-off-by:
Conor Dooley <conor.dooley@microchip.com> Reviewed-by:
-
Christian Marangi authored
Rework the handling of the CBR address and cache it. This address doesn't change and can be cached instead of reading the register every time. This is in preparation of permitting to tweak the CBR address in DT with broken SoC or bootloader. bmips_cbr_addr is defined in setup.c for each arch to keep compatibility with legacy brcm47xx/brcm63xx and generic BMIPS target. Acked-by:
-
Thomas Bogendoerfer authored
-
- 21 Jun, 2024 8 commits
-
-
Jiaxun Yang authored
Somehow those enablement bits were left over when we were adding initial Loongson-2K support. Set up basic information and select proper builtin DTB for Loongson-2K. Cc: stable@vger.kernel.org Signed-off-by:
-
Jiaxun Yang authored
Some firmware implementations require restoring ra and sp to be passed as arguments. Passing them as necessary. Fixes: 68557c59 ("MIPS: Loongson64: Implement PM suspend for LEFI firmware") Signed-off-by:
-
Jiaxun Yang authored
We should always use firmware's poweroff & reboot service if it's available as firmware may need to perform more task than platform's syscon etc. However _machine_restart & poweroff hooks are registered at low priority, which means platform reboot driver can override them. Register firmware based reboot/poweroff implementation with register_sys_off_handler with appropriate priority so that they will be prioritised. Remove _machine_halt hook as it's deemed to be unnecessary. Cc: stable@vger.kernel.org Signed-off-by:
-
Jiaxun Yang authored
cpu_hwmon is unsupported on CPUs without loongson_chiptemp register and csr. Cc: stable@vger.kernel.org Signed-off-by:
-
Jiaxun Yang authored
Some global register address variable may be missing on specific CPU type, test them before use them. Cc: stable@vger.kernel.org Signed-off-by:
-
Jiaxun Yang authored
ISA node is required by Loongson64 platforms to initialize PIO support. Kernel will hang at boot without ISA node. Cc: stable@vger.kernel.org Signed-off-by:
-
Jiaxun Yang authored
phy-mode should be rgmii-id to match hardware configuration. Also there should be a phy-handle to reference phy node. Fixes: f8a11425 ("MIPS: Loongson64: Add GMAC support for Loongson-2K1000") Cc: stable@vger.kernel.org Signed-off-by:
-
Jiaxun Yang authored
The correct interrupt line for RTC is line 8 on liointc1. Fixes: e47084e1 ("MIPS: Loongson64: DTS: Add RTC support to Loongson-2K1000") Cc: stable@vger.kernel.org Signed-off-by:
-
