- 06 Apr, 2021 40 commits
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Hans Verkuil authored
This read-only int32 control is used to test read-only controls in combination with requests. It is set by the driver to the buffer sequence counter module 256. Signed-off-by:
Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by:
Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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Stanimir Varbanov authored
Fixes an issue when issuing a stop command to the controller, negating the following firmware error. "SFR message from FW: Exception: TID = Unknown IP = 0x3b7dc FA = 0x0 cause = 0x6" Signed-off-by:
Stanimir Varbanov <stanimir.varbanov@linaro.org> Signed-off-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by:
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Dikshita Agarwal authored
Decide work mode for encoder and decoder based on different use-cases. Signed-off-by:
Dikshita Agarwal <dikshita@codeaurora.org> Signed-off-by:
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Dikshita Agarwal authored
Presently, minimum buffer count for output buffers for h264 & hevc codec is kept as 8 which might not be sufficient for few use cases so increasing the value to 18. Signed-off-by:
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Dikshita Agarwal authored
Set actual plane alignments to FW with HFI_PROPERTY_PARAM_UNCOMPRESSED_PLANE_ACTUAL_CONSTRAINTS_INFO to calculate correct buffer size. bod: Fixed fall-through error in pkt_session_set_property_6xx() switch Ensure setting format constraints on 6xx only Signed-off-by: -
Dikshita Agarwal authored
- Internal buffers required by v6 are different than v4, add new list of internal buffers for v6. - Differentiate encoder/decoder buffers for 6xx Signed-off-by:
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Dikshita Agarwal authored
Do not toggle the WRAPPER_A9SS_SW_RESET on 6xx. Signed-off-by:
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Dikshita Agarwal authored
When in vcodec_control_v4() on the 4xx path we select between one of two vcodec cores to toggle power control bits. In 6xx there is only one core which offsets the relevant control registers to a slightly different address. This patch accounts for the address offset for 6xx silicon. Signed-off-by:
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Dikshita Agarwal authored
This patch takes the downstream AXI halt routine and applies it when IS_V6() is true. bod: Converted to readl_poll_timeout() Removed poll timeout for LPI register, testing showed the value would always timeout and work, so the polling did nothing of value. Signed-off-by: -
Dikshita Agarwal authored
Vote for min clk frequency for core clks during prepare and enable clocks at boot sequence. Without this the controller clock runs at very low value (9.6MHz) which is not sufficient to boot venus. Signed-off-by:
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Bryan O'Donoghue authored
At this time there is no need to differentiate between the two, we can reuse the 4xx pm ops callback structure for 6xx. Signed-off-by:
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Bryan O'Donoghue authored
In various places in the venus codebase we have if (IS_V4()) which takes the code down paths for 4xx silicon. This logic is broadly applicable to 6xx silicon also. In this patch we add IS_V6() to various IS_V4() decision locations. Co-developed-by:
Dikshita Agarwal <dikshita@qti.qualcomm.com> Signed-off-by:
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Bryan O'Donoghue authored
On 6xx we should read wrapper cpu status from the wrapper TZ register set. Co-developed-by:
Jonathan Marek <jonathan@marek.ca> Signed-off-by:
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Dikshita Agarwal authored
This commit adds 6xx specific interrupt support, some register offsets and bitmasks differ from 4xx, which we account for in this commit. [bod: Added commit log. Moved register definition into commit] Signed-off-by:
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Dikshita Agarwal authored
This patch adds a 6xx specific boot logic. The goal is to share as much code as possible between 3xx, 4xx and 6xx silicon. We need to do a different write to WRAPPER_INTR_MASK with an additional write to CPU_CS_H2XSOFTINTEN_V6 and CPU_CS_X2RPMh_V6. The other writes are the same for 6xx and non-6xx silicon albeit at different absolute relative locations to the base of the venus address space. Signed-off-by:
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Bryan O'Donoghue authored
This commit points the IO base registers 6xx offsets when probing for 6xx hardware. Signed-off-by:
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Bryan O'Donoghue authored
6xx silicon needs to access registers from a AON base address range. This commit defines the necessary variable for later use. Signed-off-by:
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Bryan O'Donoghue authored
6xx silicon needs to access registers from a wrapper trust-zone base address range. This commit defines the necessary variable for later use. Signed-off-by:
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Bryan O'Donoghue authored
This commit adds the macro helper IS_V6() which will be used to differentiate iris2/v6 silicon from previous versions. Signed-off-by:
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Dikshita Agarwal authored
- Add X2 RPMh registers and definitions from the downstream example. - Add 6xx core power definitions - Add 6xx AON definitions - Add 6xx wrapper tz definitions - Add 6xx wrapper interrupt definitions - Add 6xx soft interrupt definitions - Define wrapper LPI register offsets Signed-off-by:
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Dikshita Agarwal authored
This commit defines a range of new base addresses for already defined blocks. - CPU_BASE_V6 - CPU_CS_BASE_V6 - CPU_IC_BASE_V6 - WRAPPER_BASE_V6 The base addresses of the blocks are slightly different for 6xx but, aside from that are layout and bit compatible. New 6xx specific block addresses will be added in separate commits. Signed-off-by:
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Bryan O'Donoghue authored
An upcoming silicon change places a number of existing blocks within the Venus at different relative offsets to the base address of IO region. In order to handle this difference this patch changes the address offsets of the registers to function as offsets relative to the relevant sub-block of registers within the IO region not the base address of the IO region. As a result of this change venus_readl() and venus_writel() are deleted. Co-developed-by:
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Bryan O'Donoghue authored
New silicon means that the pre-determined offsets we have been using in this driver no longer hold. Existing blocks of registers can exist at different offsets relative to the IO base address. This commit adds a routine to assign the IO base hooks a subsequent commit will convert from absolute to relative addressing. Signed-off-by:
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Bryan O'Donoghue authored
Adds an sm8250 compatible binding to the venus core. Co-developed-by:
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Stanimir Varbanov authored
The Venus driver has to control two reset signals related to gcc video_axi0 and videocc mvs0c for v6. Add it. Signed-off-by:
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Bryan O'Donoghue authored
Currently hfi_platform_v6.c adds a bunch of capability parameters. Reviewing downstream we can see a number of these need to be updated. techpack/video/msm/vidc/msm_vidc_platform.c :: kona_capabilities[] Signed-off-by:
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Stanimir Varbanov authored
Create CLL and Mastering display colour volume v4l2 controls for encoder, add handling of HDR10 PQ SEI packet payloads for v4. Signed-off-by:
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Stanimir Varbanov authored
Document Content Light Level and Mastering Display v4l2 colorimetry controls. Signed-off-by:
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Stanimir Varbanov authored
Introduce Content light level and Mastering display colour volume Colorimetry compound controls with relevant payload structures and validation. Signed-off-by:
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Stanimir Varbanov authored
Add a document for ext control colorimetry class. Signed-off-by:
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Stanimir Varbanov authored
Add Colorimetry control class for colorimetry controls Signed-off-by:
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Stanimir Varbanov authored
Adds support for decoder conceal color control. Signed-off-by:
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Stanimir Varbanov authored
Add decoder v4l2 control to set conceal color. Signed-off-by:
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Stanimir Varbanov authored
The property is supported from v1 and upwards. So move it to set_property_1x. Fixes: 01e869e7 ("media: venus: venc: fix handlig of S_SELECTION and G_SELECTION") Cc: stable@vger.kernel.org # v5.12 Signed-off-by:
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Stanimir Varbanov authored
It is observed that on Venus v1 the default header-mode is producing a bitstream which is not playble. Change the default header-mode to joined with 1st frame. Fixes: 002c22bd ("media: venus: venc: set inband mode property to FW.") Cc: stable@vger.kernel.org # v5.12 Signed-off-by:
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Stanimir Varbanov authored
The rate of the core clock is set through devm_pm_opp_set_rate and to avoid errors from it we have to set the name of the clock via dev_pm_opp_set_clkname. Fixes: 9a538b83 ("media: venus: core: Add support for opp tables/perf voting") Cc: stable@vger.kernel.org # v5.10+ Signed-off-by:
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Stanimir Varbanov authored
The inst function argument is != NULL only for Venus v1 and we did not migrate v1 to a hfi_platform abstraction yet. So check for instance != NULL only after hfi_platform_get returns no error. Fixes: e2992926 ("media: venus: Get codecs and capabilities from hfi platform") Cc: stable@vger.kernel.org # v5.12 Signed-off-by:
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Stanimir Varbanov authored
The Venus v1 behaves differently comparing with the other Venus version in respect to capability parsing and when they are send to the driver. So we don't need to initialize hfi parser for multiple invocations like what we do for > v1 Venus versions. Fixes: 10865c98 ("media: venus: parser: Prepare parser for multiple invocations") Cc: stable@vger.kernel.org # v5.10+ Signed-off-by:
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Dikshita Agarwal authored
Add support for below LTR controls in encoder: - V4L2_CID_MPEG_VIDEO_LTR_COUNT - V4L2_CID_MPEG_VIDEO_FRAME_LTR_INDEX - V4L2_CID_MPEG_VIDEO_USE_LTR_FRAMES Signed-off-by:
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Dikshita Agarwal authored
Long Term Reference (LTR) frames are the frames that are encoded sometime in the past and stored in the DPB buffer list to be used as reference to encode future frames. This change adds controls to enable this feature. Signed-off-by:
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