- 28 Jun, 2022 17 commits
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Dave Stevenson authored
DSI0 seemingly had very little or no testing as a load of the register mappings were incorrect/missing, so host transfers always timed out due to enabling/checking incorrect bits in the interrupt enable and status registers. Fixes: 4078f575 ("drm/vc4: Add DSI driver") Signed-off-by:
Dave Stevenson <dave.stevenson@raspberrypi.com> Link: https://lore.kernel.org/r/20220613144800.326124-16-maxime@cerno.techSigned-off-by:
Maxime Ripard <maxime@cerno.tech>
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Dave Stevenson authored
vc4_dsi was registering both dsi0 and dsi1 as VC4_ENCODER_TYPE_DSI1 which seemed to work OK for a single DSI display, but fails if there are two DSI displays connected. Update to register the correct type. Fixes: 4078f575 ("drm/vc4: Add DSI driver") Signed-off-by:
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Dave Stevenson authored
For slightly unknown reasons, dsi0 takes a different pixel format to dsi1, and that has to be set in the pixel valve. Amend the setup accordingly. Fixes: a86773d1 ("drm/vc4: Add support for feeding DSI encoders from the pixel valve.") Signed-off-by:
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Dave Stevenson authored
The divider calculations tried to find the divider just faster than the clock requested. However if it required a divider of 7 then the for loop aborted without handling the "error" case, and could end up with a clock lower than requested. The integer divider from parent PLL to DSI clock is also capable of going up to /255, not just /7 that the driver was trying. This allows for slower link frequencies on the DSI bus where the resolution permits. Correct the loop so that we always have a clock greater than requested, and covering the whole range of dividers. Fixes: 86c1b9ef ("drm/vc4: Adjust modes in DSI to work around the integer PLL divider.") Signed-off-by:
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Dave Stevenson authored
On Pi0-3 the driver allocates a buffer and requests a DMA channel because the ARM can't write to DSI1's registers directly. However, we never release that buffer or channel. Let's add a device-managed action to release each. Fixes: 4078f575 ("drm/vc4: Add DSI driver") Signed-off-by:
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Dave Stevenson authored
In a couple of error/incomplete configuration cases, the DPI_FORMAT bits wouldn't get set. Enforce our RGB888 default in all these cases. Signed-off-by:
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Dave Stevenson authored
DRM provides flags for inverting pixel clock and output enable signals, but these were not mapped to the relevant registers. Add those mappings. Signed-off-by:
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Dave Stevenson authored
The hardware can combine H&V syncs onto the output enable line as composite syncs, so add the relevant configuration to do that. Signed-off-by:
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Dave Stevenson authored
This allows easy analysis of display lists when debugging. Signed-off-by:
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Dave Stevenson authored
Move from only supporting the default of pre-multiplied alpha to supporting user specified blend mode using the standardised property. Signed-off-by:
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Dave Stevenson authored
The current plane margin calculation code clips the right and bottom edges of the range based using the left and top margins. This is obviously wrong, so let's fix it. Fixes: 666e7358 ("drm/vc4: Take margin setup into account when updating planes") Signed-off-by:
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Dom Cobley authored
There is little harm in ignoring fractional coordinates (they just get truncated). Without this: modetest -M vc4 -F tiles,gradient -s 32:1920x1080-60 -P89@74:1920x1080*.1.1@XR24 is rejected. We have the same issue in Kodi when trying to use zoom options on video. Note: even if all coordinates are fully integer. e.g. src:[0,0,1920,1080] dest:[-10,-10,1940,1100] it will still get rejected as drm_atomic_helper_check_plane_state uses drm_rect_clip_scaled which transforms this to fractional src coords Fixes: 21af94cf ("drm/vc4: Add support for scaling of display planes.") Signed-off-by:
Dom Cobley <popcornmix@gmail.com> Link: https://lore.kernel.org/r/20220613144800.326124-5-maxime@cerno.techSigned-off-by:
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Maxime Ripard authored
The core clock computation takes into account both the load due to the input (ie, planes) and its output (ie, encoders). However, while the input load needs to consider all the planes, and thus sum all of their associated loads, the output happens mostly in parallel. Therefore, we need to consider only the maximum of all the output loads, and not the sum like we were doing. This resulted in a clock rate way too high which could be discarded for being too high by the clock framework. Since recent changes, the clock framework will even downright reject it, leading to a core clock being too low for its current needs. Fixes: 16e10105 ("drm/vc4: Increase the core clock based on HVS load") Signed-off-by:
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Maxime Ripard authored
We currently ignore the clk_set_min_rate return code assuming it would succeed. However, it can fail if we ask for a rate higher than the current maximum for example. Since we can't fail in atomic_commit, at least warn on failure. Signed-off-by:
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Dave Stevenson authored
vc4_drv isn't necessarily under the /soc node in DT as it is a virtual device, but it is the one that does the allocations. The DMA addresses are consumed by primarily the HVS or V3D, and those require VideoCore cache alias address mapping, and so will be under /soc. During probe find the a suitable device node for HVS or V3D, and adopt the DMA configuration of that node. Cc: <stable@vger.kernel.org> Signed-off-by:
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Imre Deak authored
The driver expects the pitch of the Intel CCS CC color planes to be 64 bytes aligned, adjust the modifier descriptions accordingly. Cc: Nanley Chery <nanley.g.chery@intel.com> Signed-off-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
Nanley Chery <nanley.g.chery@intel.com> Reviewed-by:
Jordan Justen <jordan.l.justen@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220623144955.2486736-1-imre.deak@intel.com
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Marek Vasut authored
Replace apprpriately with appropriately. Fixes: 1e4d84c6 ("drm/doc: Polish plane composition property docs") Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Benjamin Gaignard <benjamin.gaignard@linaro.org> Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Maxime Ripard <maxime@cerno.tech> Cc: Sean Paul <seanpaul@chromium.org> Cc: Simon Ser <contact@emersion.fr> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Simon Ser <contact@emersion.fr> Reviewed-by:
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- 27 Jun, 2022 18 commits
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Yannick Fertre authored
The latest hardware version (0x40100) supports a hardware threshold register (aka FUTR) to trigger a fifo underrun interrupt. A software threshold has been implemented for other hardware versions. The threshold is set to 128 by default. Signed-off-by:
Yannick Fertre <yannick.fertre@foss.st.com> Signed-off-by:
Philippe Cornu <philippe.cornu@foss.st.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220603134654.594373-1-yannick.fertre@foss.st.com
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Yannick Fertre authored
Support of vertical & horizontal mirroring features thanks to the plane rotation property. Signed-off-by:
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Yannick Fertre authored
Zpos property is immutable for all hardware versions except the last version (0x40100) which support the blending order feature (dynamic z-order). Signed-off-by:
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Yannick Fertre authored
Fix issues reported by checkpatch.pl: - Braces {} should be used on all arms - Blank lines Signed-off-by:Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> Signed-off-by:
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Yannick Fertre authored
Remove error message about scaling & replace it by a debug message to avoid too much error. Signed-off-by:
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Yannick Fertre authored
All plans must be disabled before the CRTC shutdown helping the crtc to restart from a clean situation (without unwanted planes already enable). Signed-off-by:
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José Expósito authored
Explain how to run the KUnit tests present in the DRM subsystem and clarify why the UML-only options were not added to the configuration file present in drivers/gpu/drm/.kunitconfig [1] [2]. [1] https://lore.kernel.org/dri-devel/CABVgOSn8i=LO5p7830h2XU1Jgg0KrN0qTnxkOMhf1oTgxjaKKw@mail.gmail.com/ [2] https://lore.kernel.org/dri-devel/CAGS_qxqpiCim_sy1LDK7PLwVgWf-LKW+uNFTGM=T7ydk-dYcEw@mail.gmail.com/Reviewed-by:
Javier Martinez Canillas <javierm@redhat.com> Reviewed-by:
David Gow <davidgow@google.com> Acked-by:
Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by:
José Expósito <jose.exposito89@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220620160640.3790-4-jose.exposito89@gmail.com
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José Expósito authored
Test the conversion from XRGB8888 to RGB332. What is tested? - Different values for the X in XRGB8888 to make sure it is ignored - Different clip values: Single pixel and full and partial buffer - Well known colors: White, black, red, green, blue, magenta, yellow and cyan - Other colors: Randomly picked - Destination pitch How to run the tests? $ ./tools/testing/kunit/kunit.py run --kunitconfig=drivers/gpu/drm/tests \ --kconfig_add CONFIG_VIRTIO_UML=y \ --kconfig_add CONFIG_UML_PCI_OVER_VIRTIO=y Suggested-by: -
José Expósito authored
Add a helper macro to initialize a rectangle from x, y, width and height information. Reviewed-by:
Jani Nikula <jani.nikula@intel.com> Reviewed-by:
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Thomas Zimmermann authored
As the CRTC requires a primary plane for display, ensure that the primary plane is enabled with the CRTC. Use drm_atomic_helper_check_crtc_state(). Add all affected planes to the atomic state so that their state will be checked as well. Signed-off-by:
Jocelyn Falempe <jfalempe@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220617103226.25617-4-tzimmermann@suse.de
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Thomas Zimmermann authored
Simple-KMS helpers guarantee that the CRTC and plane enable flags are synchronized. Implement this with atomic helpers drm_atomic_helper_check_crtc_state() on the CRTC side, and drm_atomic_helper_check_plane_state() on the plane side. Signed-off-by:
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Thomas Zimmermann authored
Add drm_atomic_helper_check_crtc_state(), which contains tests common to many CRTCs. The first added test verifies that an enabled CRTC has at least one enabled primary plane. Signed-off-by:
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Thomas Zimmermann authored
Clip memory range to screen-buffer size to avoid out-of-bounds access in fbdev deferred I/O's damage handling. Fbdev's deferred I/O can only track pages. From the range of pages, the damage handler computes the clipping rectangle for the display update. If the fbdev screen buffer ends near the beginning of a page, that page could contain more scanlines. The damage handler would then track these non-existing scanlines as dirty and provoke an out-of-bounds access during the screen update. Hence, clip the maximum memory range to the size of the screen buffer. While at it, rename the variables min/max to min_off/max_off in drm_fb_helper_deferred_io(). This avoids confusion with the macros of the same name. Reported-by:
Nuno Gonçalves <nunojpg@gmail.com> Signed-off-by:
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Alex Williamson authored
Console drivers can create conflicts with PCI resources resulting in userspace getting mmap failures to memory BARs. This is especially evident when trying to re-use the system primary console for userspace drivers. Use the aperture helpers to remove these conflicts. v3: * call aperture_remove_conflicting_pci_devices() Reported-by:
Laszlo Ersek <lersek@redhat.com> Suggested-by:
Gerd Hoffmann <kraxel@redhat.com> Signed-off-by:
Alex Williamson <alex.williamson@redhat.com> Signed-off-by:
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Thomas Zimmermann authored
Implement DRM's aperture helpers under video/ for sharing with other sub-systems. Remove DRM-isms from the interface. The helpers track the ownership of framebuffer apertures and provide hand-over from firmware, such as EFI and VESA, to native graphics drivers. Other subsystems, such as fbdev and vfio, also have to maintain ownership of framebuffer apertures. Moving DRM's aperture helpers to a more public location allows all subsystems to interact with each other and share a common implementation. The aperture helpers are selected by the various firmware drivers within DRM and fbdev, and the VGA text-console driver. The original DRM interface is kept in place for use by DRM drivers. v3: * prefix all interfaces with aperture_ (Javier) * rework and simplify documentation (Javier) * rename struct dev_aperture to struct aperture_range * rebase onto latest DRM * update MAINTAINERS entry Signed-off-by:
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Thomas Zimmermann authored
There will be more DRM drivers for firmware-provided framebuffers. Use the existing entry for simpledrm instead of adding a new one for each driver. Also add DRM's aperture helpers, which are part of the driver's infrastructure. Signed-off-by:
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Jocelyn Falempe authored
With an AST2600, the screen is garbage when going out of suspend. This is because color settings are lost, and not restored on resume. Force the color settings on DPMS_ON, to make sure the settings are correct. I didn't write this code, it comes from the out-of-tree aspeed driver v1.13 https://www.aspeedtech.com/support_driver/Signed-off-by:
Venkat Tadikonda <venkateswara.rao@intel.com> Reviewed-by:
Lyude Paul <lyude@redhat.com> Acked-by:
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Miaoqian Lin authored
Every iteration of for_each_available_child_of_node() decrements the reference counter of the previous node. There is no decrement when break out from the loop and results in refcount leak. Add missing of_node_put() to fix this. Fixes: 5fc537bf ("drm/mcde: Add new driver for ST-Ericsson MCDE") Signed-off-by:
Miaoqian Lin <linmq006@gmail.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20220525115411.65455-1-linmq006@gmail.com
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- 24 Jun, 2022 5 commits
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Bo Liu authored
Use ida_alloc_xxx()/ida_free() instead of ida_simple_get()/ida_simple_remove(). The latter is deprecated and more verbose. Signed-off-by:
Bo Liu <liubo03@inspur.com> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20220617082319.7599-1-liubo03@inspur.com Link: https://patchwork.freedesktop.org/patch/msgid/20220621190055.8323-1-jiangjian@cdjrlc.com
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Joel Selvaraj authored
Add DRM panel driver for EBBG FT8719 6.18" 2246x1080 DSI video mode panel, which can be found on some Xiaomi Poco F1 phones. The panel's backlight is managed through QCOM WLED driver. Signed-off-by:
Joel Selvaraj <jo@jsfamily.in> Reviewed-by:
Sam Ravnborg <sam@ravnborg.org> Signed-off-by:
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Joel Selvaraj authored
A helper macro that can be used to simplify sending DCS commands. It is useful in scenarios like panel initialization which can sometimes involve sending lot of DCS commands. Signed-off-by:
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Joel Selvaraj authored
Add bindings for the EBBG FT8719 6.18" 2246x1080 DSI video mode panel, which can be found on some Xiaomi Poco F1 phones. The backlight is managed through the QCOM WLED driver. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
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Joel Selvaraj authored
Add a prefix for EBBG. They manufacture displays which are used in some Xiaomi phones, but I could not find much details about the company. Signed-off-by:
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