- 19 Dec, 2023 40 commits
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Matt Roper authored
The total number of GTs supported by a platform should be one primary GT, one media GT (if media version >= 13), and a number of remote tile GTs dependent on the graphics IP present. Express this more clearly in the device setup. Note that xe->info.tile_count is inaccurately named; the rest of the driver treats this as the GT count, not just the tile count. This will need to be cleaned up at some point down the road. Reviewed-by:
Lucas De Marchi <lucas.demarchi@intel.com> Link: https://lore.kernel.org/r/20230406235621.1914492-6-matthew.d.roper@intel.comSigned-off-by:
Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
Rodrigo Vivi <rodrigo.vivi@intel.com>
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Matt Roper authored
Break the top-level platform_engine_mask field into separate hw_engine_mask fields in the graphics and media structures. Since hardware has more flexibility to mix-and-match IP versions going forward, this allows each IP to list exactly which engines it provides; the final per-GT engine list can then be constructured from those: * On platforms without a standalone media GT (i.e., media IP versions prior to 13), the primary GT's engine list is the union of the graphics IP's engine list and the media IP's engine list. * Otherwise, GT0's engine list is the graphics IP's engine list. * For GT1 and beyond, the type of GT determines which IP's engine list is used. Reviewed-by:
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Matt Roper authored
Most of the traits currently in the device descriptor structures are either tied to the graphics IP or should be inferred from the graphics IP. This becomes important on MTL and beyond where IP versions are supposed to be detected from the hardware's GMD_ID registers rather than mapped from PCI devid. Engine masks are left where they are for now; they'll be dealt with separately in a future patch. Reviewed-by:
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Matt Roper authored
Set require_force_probe explicitly in each platform's description structure rather than embedding it within the FOO_FEATURES macros. Even though we expect all platforms currently supported by the Xe driver to be under force_probe protection, this will help prepare for some other upcoming restructuring. Reviewed-by:
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Matt Roper authored
Rather than storing all characteristics for an entire platform in the xe_device_desc structure, create secondary graphics and media structures to hold traits and feature flags specific to those IPs. This will eventually allow us to assign the graphics and media characteristics at runtime based on the contents of the relevant GMD_ID registers. For now, just move the IP versions into the new structures to keep things simple. Other IP-specific fields will migrate to these structures in future patches. Note that there's one functional change introduced by this: previously PVC was recognized as media version 12.60. That's technically true, but in practice the media engines are fused off on all production hardware. By simply not assigning a media IP structure to PVC it will effectively be treated as IP version 0.0 now (which the rest of the driver should treat as non-existent media). v2: - Split the new structures out to their own header. This will ease the addition of KUnit tests later. Reviewed-by:
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Lucas De Marchi authored
When debugging issues related to GuC/HuC, it's important to know what is the firmware version being used. The version from the filename can't be relied upon, also because it normally only contains the major version (except for the ones under experimental support). Log the version from the blob after reading the CSS header. Example: xe 0000:03:00.0: [drm] Using GuC firmware (70.5) from i915/dg2_guc_70.bin Signed-off-by:
Matthew Brost <matthew.brost@intel.com> Link: https://lore.kernel.org/r/20230405224725.1993719-1-lucas.demarchi@intel.comSigned-off-by:
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Matthew Brost authored
If CCS0 was fused we did not write this register thus CCS engine were not enabled resulting in driver load failures. Signed-off-by:
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Lucas De Marchi authored
Update the logic to autoselect GuC/HuC for the platforms with the following improvements: - Document what is the firmware file that is expected to be loaded and what is checked from blob headers - When the platform is under force-probe it's desired to enforce the full-version requirement so the correct firmware is used before widespread adoption and backward-compatibility commitments - Directory from which we expect firmware blobs to be available in upstream linux-firmware repository depends on the platform: for the ones supported by i915 it uses the i915/ directory, but the ones expected to be supported by xe, it's on the xe/ directory. This means that for platforms in the intersection, the firmware is loaded from a different directory, but that is not much important in the firmware repo and it avoids firmware duplication. - Make the table with the firmware definitions clearly state the versions being expected. Now with macros to select the version it's possible to choose between full-version/major-version for GuC and full-version/no-version for HuC. These are similar to the macros used in i915, but implemented in a slightly different way to avoid duplicating the macros for each firmware/type and functionality, besides adding the support for different directories. - There is no check added regarding force-probe since xe should reuse the same firmware files published for i915 for past platforms. This can be improved later with additional kunit checking against a hardcoded list of platforms that falls in this category. - As mentioned in the TODO, the major version fallback was not implemented before as currently each platform only supports one major. That can be easily added later. - GuC version for MTL and PVC were updated to 70.6.4, using the exact full version, while the After this the GuC firmware used by PVC changes to pvc_guc_70.5.2.bin since it's using a file not published yet. Signed-off-by:
Anusha Srivatsa <anusha.srivatsa@intel.com> Link: https://lore.kernel.org/r/20230324051754.1346390-4-lucas.demarchi@intel.comSigned-off-by:
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Lucas De Marchi authored
In order to avoid mistakes when populating the workarounds, it's good to be able to test if the entries added are all compatible for a certain platform. The platform itself is not needed as long as we create fake devices with enough configuration for the RTP helpers to process the tables. Common mistakes that can be avoided: - Entries clashing the bitfields being updated - Register type being mixed (MCR vs regular / masked vs regular) - Unexpected errors while adding the reg_sr entry To test, inject a duplicate entry in gt_was, but with platform == tigerlake rather than the currenct graphics version check: { XE_RTP_NAME("14011059788"), XE_RTP_RULES(PLATFORM(TIGERLAKE)), XE_RTP_ACTIONS(SET(GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE)) }, This produces the following result: $ ./tools/testing/kunit/kunit.py run \ --kunitconfig drivers/gpu/drm/xe/.kunitconfig xe_wa [14:18:02] Starting KUnit Kernel (1/1)... [14:18:02] ============================================================ [14:18:02] ==================== xe_wa (1 subtest) ===================== [14:18:02] ======================== xe_wa_gt ========================= [14:18:02] [drm:xe_reg_sr_add] *ERROR* Discarding save-restore reg 9550 (clear: 00000200, set: 00000200, masked: no): ret=-22 [14:18:02] # xe_wa_gt: ASSERTION FAILED at drivers/gpu/drm/xe/tests/xe_wa_test.c:116 [14:18:02] Expected gt->reg_sr.errors == 0, but [14:18:02] gt->reg_sr.errors == 1 (0x1) [14:18:02] [FAILED] TIGERLAKE (B0) [14:18:02] [PASSED] DG1 (A0) [14:18:02] [PASSED] DG1 (B0) ... Signed-off-by:Michał Winiarski <michal.winiarski@intel.com> Link: https://lore.kernel.org/r/20230401085151.1786204-8-lucas.demarchi@intel.comSigned-off-by:
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Lucas De Marchi authored
Add some basic unit tests for rtp. This is intended to prove the functionality of the rtp itself, like coalescing entries, rejecting non-disjoint values, etc. Contrary to the other tests in xe, this is a unit test to test the sw-side only, so it can be executed on any machine - it doesn't interact with the real hardware. Running it produces the following output: $ ./tools/testing/kunit/kunit.py run --raw_output-kunit \ --kunitconfig drivers/gpu/drm/xe/.kunitconfig xe_rtp ... [01:26:27] Starting KUnit Kernel (1/1)... KTAP version 1 1..1 KTAP version 1 # Subtest: xe_rtp 1..1 KTAP version 1 # Subtest: xe_rtp_process_tests ok 1 coalesce-same-reg ok 2 no-match-no-add ok 3 no-match-no-add-multiple-rules ok 4 two-regs-two-entries ok 5 clr-one-set-other ok 6 set-field [drm:xe_reg_sr_add] *ERROR* Discarding save-restore reg 0001 (clear: 00000001, set: 00000001, masked: no): ret=-22 ok 7 conflict-duplicate [drm:xe_reg_sr_add] *ERROR* Discarding save-restore reg 0001 (clear: 00000003, set: 00000000, masked: no): ret=-22 ok 8 conflict-not-disjoint [drm:xe_reg_sr_add] *ERROR* Discarding save-restore reg 0001 (clear: 00000002, set: 00000002, masked: no): ret=-22 [drm:xe_reg_sr_add] *ERROR* Discarding save-restore reg 0001 (clear: 00000001, set: 00000001, masked: yes): ret=-22 ok 9 conflict-reg-type # xe_rtp_process_tests: pass:9 fail:0 skip:0 total:9 ok 1 xe_rtp_process_tests # Totals: pass:9 fail:0 skip:0 total:9 ok 1 xe_rtp ... Note that the ERRORs in the kernel log are expected since it's testing incompatible entries. v2: - Use parameterized table for tests (Michał Winiarski) - Move everything to the xe_rtp_test.ko and only add a few exports to the right namespace - Add more tests to cover FIELD_SET, CLR, partially true rules, etc Signed-off-by: -
Lucas De Marchi authored
When there's an entry that is dropped when xe_reg_sr_add(), there's not much we can do other than reporting the error - it's for certain a driver issue or conflicting workarounds/tunings. Save the number of errors to be used later by kunit to report where it happens. Signed-off-by:
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Lucas De Marchi authored
Instead of requiring tests to initialize a fake device an keep it in sync with xe_pci.c when it's platform-dependent, export a function from xe_pci.c to be used and piggy back on the device info creation. For simpler tests that don't need any specific platform and just need a fake xe device to pass around, xe_pci_fake_device_init_any() can be used. Signed-off-by:
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Lucas De Marchi authored
Instead of simply using EXPORT_SYMBOL() to export the functions needed in xe.ko to be be called across modules, use EXPORT_SYMBOL_IF_KUNIT() which will export the symbol under the EXPORTED_FOR_KUNIT_TESTING namespace. This avoids accidentally "leaking" these functions and letting them be called from outside the kunit tests. If these functiosn are accidentally called from another module, they receive a modpost error like below: ERROR: modpost: module XXXXXXX uses symbol xe_ccs_migrate_kunit from namespace EXPORTED_FOR_KUNIT_TESTING, but does not import it. Signed-off-by:
Mauro Carvalho Chehab <mchehab@kernel.org> Link: https://lore.kernel.org/r/20230401085151.1786204-4-lucas.demarchi@intel.comSigned-off-by:
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Lucas De Marchi authored
Move code out of xe_pci.[ch] into tests/*.[ch], like is done in other similar compilation units. Even if this is not part of "tests for xe_pci.c", they are functions exported and required by other tests. It's better not to clutter the module headers and sources with them. Signed-off-by:
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Lucas De Marchi authored
Extract the part setting up from xe->info from xe_pci_probe() into its own function. This pairs nicely with the display counterpart, avoids info initialization to be placed elsewhere and helps future improvements to build fake devices for tests. While at it, normalize the names a little bit: the _get() suffix may be mistaken by lock-related operation, so rename the function to "find_subplatform()". Also rename the variable to subplatform_desc to make it easier to understand, even if longer. Signed-off-by:
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Matt Roper authored
Although our only multi-tile platform today (PVC) doesn't support display, it's possible that some future multi-tile platform will. If/when this happens, display interrupts (both traditional display and ASLE backlight interrupts raised as a Gunit interrupt) should be delivered to the primary tile. Save away tile0's master_ctl value so that it can still be used for display interrupt handling after the GT loop. Reviewed-by:
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Matt Roper authored
Although the hardware team has set aside some register bits for extra media engines, no platform supported by the Xe driver today has VCS4-7 or VECS2-3. Drop the corresponding code (which was already commented out); we can bring it back easily enough if such engines show up on a future platform. Reviewed-by:
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Matt Roper authored
The remaining "gen11_*" IRQ functions are common to all platforms supported by the Xe driver. Drop the unnecessary prefix. Reviewed-by:
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Matt Roper authored
Platforms supported by the Xe driver handle top-level interrupts in one of two ways: - Xe_LP platforms only have a "graphics master" register and lack a "master tile" register, so top-level interrupt detection and enable/disable happens in the graphics master. - Xe_LP+ (aka DG1) and beyond have a "master tile" interrupt register that controls the enable/disable of top-level interrupts and must also be consulted to determine which tiles have received interrupts before the driver moves on the process the graphics master register. For functions that are only relevant to the first set of platforms, rename the function prefix to Xe_LP since "gen11" doesn't make sense in the Xe driver. Also add some comments briefly describing the two top-level handlers. Reviewed-by:
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Matt Roper authored
Any interrupt registers that were introduced by platforms i915 considered to be "gen11" or "gen12" are present on all platforms that the Xe driver supports; drop the unnecessary prefixes. While working in the area, also convert a few open-coded bit manipulations over to REG_BIT and REG_FIELD_GET notation. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by:
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Matt Roper authored
It's no longer necessary to wrap these operations in macros; a simple function will suffice. Also switch to function names that more clearly describe what operation is being performed: unmask_and_enable() and mask_and_disable(). Reviewed-by:
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Matt Roper authored
For cases where IRQ_INIT and IRQ_RESET are used, the relevant interrupt registers are always consecutive and ordered ISR, IMR, IIR, IER. Adding helpers to look these up from a base offset will let us eliminate some of the CPP pasting and simplify other upcoming patches. v2: - s/_REGS/_OFFSET/ for consistency. (Lucas) - Move IMR/IIR/IER helpers into xe_irq.c; they aren't needed anywhere else. (Lucas) Cc: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by:
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Matt Roper authored
"Gen" terminology should be avoided in the Xe driver and "gen3" refers to platforms that are 9 (!!) graphics generations earlier than the oldest supported by the Xe driver, so this prefix really doesn't make sense. Reviewed-by:
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Chang, Bruce authored
Currently, unload pvc driver will generate a null dereference and the call stack is as below. [ 4850.618000] Call Trace: [ 4850.620740] <TASK> [ 4850.623134] ttm_bo_cleanup_memtype_use+0x3f/0x50 [ttm] [ 4850.628661] ttm_bo_release+0x154/0x2c0 [ttm] [ 4850.633317] ? drm_buddy_fini+0x62/0x80 [drm_buddy] [ 4850.638487] ? __kmem_cache_free+0x27d/0x2c0 [ 4850.643054] ttm_bo_put+0x38/0x60 [ttm] [ 4850.647190] xe_gem_object_free+0x1f/0x30 [xe] [ 4850.651945] drm_gem_object_free+0x1e/0x30 [drm] [ 4850.656904] ggtt_fini_noalloc+0x9d/0xe0 [xe] [ 4850.661574] drm_managed_release+0xb5/0x150 [drm] [ 4850.666617] drm_dev_release+0x30/0x50 [drm] [ 4850.671209] devm_drm_dev_init_release+0x3c/0x60 [drm] There are a couple issues, but the main one is due to TTM has only one TTM_PL_TT region, but since pvc has 2 tiles and tries to setup 1 TTM_PL_TT each tile. The second will overwrite the first one. During unload time, the first tile will reset the TTM_PL_TT manger and when the second tile is trying to free Bo and it will generate the null reference since the TTM manage is already got reset to 0. The fix is to use one global TTM_PL_TT manager. v2: make gtt mgr global and change the name to sys_mgr Cc: Stuart Summers <stuart.summers@intel.com> Cc: Matthew Brost <matthew.brost@intel.com> Cc: Vivi, Rodrigo <rodrigo.vivi@intel.com> Signed-off-by:
Bruce Chang <yu.bruce.chang@intel.com> Reviewed-by:
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Lucas De Marchi authored
Platform order in enum xe_platform started to be used by some parts of the code, like the GuC/HuC firmware loading logic. The order itself is not very important, but it's better to follow a convention: as was documented in the comment above the enum, reorder the platforms by graphics version. While at it, remove the gen terminology. v2: - Use "graphics version" instead of chronological order (Matt Roper) - Also change pciidlist to follow the same order - Remove "gen" from comments around enum xe_platform Signed-off-by:
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Niranjana Vishwanathapura authored
In xe_migrate functions, use proper vram io offset of the tiles while calculating addresses. Reviewed-by:
Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> Signed-off-by:
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Niranjana Vishwanathapura authored
In xe_migrate_sanity_kunit test, use correct expected value as the expected value was not only used for the xe_migrate_clear(), but also for the xe_migrate_copy() operation. v2: Add 'Fixes' tag and update commit text Fixes: 11a2407e ("drm/xe: Stop accepting value in xe_migrate_clear") Reviewed-by:
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Niranjana Vishwanathapura authored
In xe_migrate_sanity_kunit test, use proper batch base address by considering usm case. Reviewed-by:
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Lucas De Marchi authored
The rev field is always 0 so it ends up never used. In i915 it was introduced because of CML: up to rev 5 it reuses the guc and huc firmware blobs from KBL. After that there is a specific firmware for that platform. This can be reintroduced later if ever needed. With the removal of revid the packed attribute in uc_fw_platform_requirement, which is there only for reducing the space these tables take, can also be removed since it has even more limited usefulness: currently there's only padding of 2 bytes. Remove the attribute to avoid the unaligned access. $ pahole -C uc_fw_platform_requirement build64/drivers/gpu/drm/xe/xe_uc_fw.o struct uc_fw_platform_requirement { enum xe_platform p; /* 0 4 */ const struct uc_fw_blob blob; /* 4 10 */ /* size: 16, cachelines: 1, members: 2 */ /* padding: 2 */ /* last cacheline: 16 bytes */ }; Signed-off-by: -
Matt Roper authored
The MI_BATCH_BUFFER_END is already added automatically by __xe_bb_create_job(); including it in the construction of the workaround batchbuffer results in an unnecessary duplicate. Link: https://lore.kernel.org/r/20230329173334.4015124-4-matthew.d.roper@intel.comSigned-off-by:
José Roberto de Souza <jose.souza@intel.com> Signed-off-by:
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Matt Roper authored
We should WARN (not BUG) when creating a job if the batchbuffer does not have sufficient space and padding. The hardware prefetch requirements should also be considered. Link: https://lore.kernel.org/r/20230329173334.4015124-3-matthew.d.roper@intel.comSigned-off-by:
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Matt Roper authored
The hardware prefetches several cachelines of data from batchbuffers before they are parsed. This prefetching only stops when the parser encounters an MI_BATCH_BUFFER_END instruction (or a nested MI_BATCH_BUFFER_START), so we must ensure that there is enough padding at the end of the batchbuffer to prevent the prefetcher from running past the end of the allocation and potentially faulting. Bspec: 45717 Link: https://lore.kernel.org/r/20230329173334.4015124-2-matthew.d.roper@intel.comSigned-off-by:
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Matthew Brost authored
Add some error messages describing the problem when xe_gt_record_default_lrcs fails. Signed-off-by:
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Chang, Bruce authored
In general, this is due to FW load failure, should just report error and fail the probe so that user can easily retry again. Reviewed-by:
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Matt Roper authored
The tables are only used within this file; there's no reason for them not to be static. Reviewed-by:
Nirmoy Das <nirmoy.das@intel.com> Link: https://lore.kernel.org/r/20230327175824.2967914-1-matthew.d.roper@intel.comSigned-off-by:
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Matthew Auld authored
Get rid of some of the duplication here. In a future patch we need to also consider [fpfn, lpfn], so better adjust in only one place. Suggested-by:
Matthew Auld <matthew.auld@intel.com> Reviewed-by:
Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Signed-off-by:
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Matthew Auld authored
So we don't have to keep repeating VRAM0 | VRAM1. Also if there are ever more instances, then we have less places to update. Suggested-by:
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Matt Roper authored
Starting with MTL, the number of entries in the PAT table increased to 16. The register offset jumped between index 7 and index 8, so a slight adjustment is needed to ensure the PAT_INDEX macros select the proper offset for the upper half of the table. Note that although there are 16 registers in the hardware, the driver is currently only asked to program the first 5, and we leave the rest at their hardware default values. That means we don't actually touch the upper half of the PAT table in the driver today and this patch won't have any functional effect [yet]. Bspec: 44235 Reviewed-by:
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Matt Roper authored
Re-sync our MTL PAT table with the bspec. 1-way coherency should only be set on table entry 3. We do not want an incorrect setting here to accidentally paper over other bugs elsewhere in the driver. Bspec: 45101 Reviewed-by:
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Matt Roper authored
Replace the deprecated "GEN" terminology in the PAT definitions. Acked-by:
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