- 27 Aug, 2018 40 commits
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Rex Zhu authored
Original 500ms delay seems a bit large. Change to 100 ms suggested by Christian. Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Vitaly Prosyak authored
This check avoids potential bugs related to gamma. Signed-off-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
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Vitaly Prosyak authored
[Why] Optimize gamma programming [How] Use ROM for optimization when it is possible. Use RAM only when it is necessary. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Nikola Cornij authored
[why] There is currently a dependency on the order in which tests are executed. This is because the non-relevant state info is being printed, which results in the output based on the state from the previous test. [how] Print DPP DTN log only if the pipe is enabled. In addition to the affected per-submission DTN golden logs, included in this change is also DTN golden log update for pre-submission tests. The other DTN golden logs affected by this change will be updated upon nightly test run (which will generate the updated DTN logs). Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
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Martin Tsai authored
[why] We didn't transfer the camera/video viewport coordinate when doing rotation and mirror. [how] To correct the viewport coordinate in calculate_viewport(). Signed-off-by:
Martin Tsai <Martin.Tsai@amd.com> Reviewed-by:
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Mikita Lipski authored
[why] In case if edid is null or corrupted we need to manually add a single failsafe mode (640x480). If zero modes returned DRM adds a different failsafe mode that is not accepted by DP 1.2 compliance test [how] Return the number of modes manually added Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
Sun peng Li <Sunpeng.Li@amd.com> Acked-by:
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Huang Rui authored
Demangle amdgpu.h. Signed-off-by:
Huang Rui <ray.huang@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Huang Rui authored
Demangle amdgpu.h. Signed-off-by:
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Huang Rui authored
Demangle amdgpu.h. Signed-off-by:
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Huang Rui authored
Demangle amdgpu.h. Furthermore, SDMA is used for moving and clearing the data buffer, so the header also need be included in ttm. Signed-off-by:
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Huang Rui authored
Demangle amdgpu.h Signed-off-by:
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Huang Rui authored
Demangle amdgpu.h Signed-off-by:
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Rex Zhu authored
gfx off support in smu can be via powergate_gfx interface. so remove the gfx_off_control interface. Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Rex Zhu authored
this patch is a workaround for the gpu hang at video begin/end time if gfx off is enabled. Reviewed-by:
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Rex Zhu authored
use amdgpu_gfx_off_ctrl function so driver can arbitrate whether the gfx ip can be power off or power on. Reviewed-by:
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Rex Zhu authored
delay to enable gfx off feature to avoid gfx on/off frequently suggested by Alex and Evan. Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Rex Zhu authored
v2: 1. drop the special handling for the hw IP suggested by hawking and Christian. 2. refine the variable name suggested by Flora. This funciton as the entry of gfx off feature. we arbitrat gfx off feature enable/disable in this function. Reviewed-by: -
Nicholas Kazlauskas authored
[Why] If the hardware supports DFS bypass it will always be enabled after creation of the DCCG. DFS bypass should only be enabled when the current stream consists of a single embedded panel and the minimum display clock is below the DFS bypass threshold. [How] Add a function to the DCCG table that updates the DFS bypass state when setting the bandwidth. If the DFS bypass state is changed, the clock needs to be reprogrammed to reflect this before the DPREFCLK is updated for audio endpoints. The existing display clock value is used as the target display clock value when reprogramming since the resulting change will be equal or larger to the current value. These changes only specifically target dce110 but do offer a framework for support on other applicable targets. Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
David Francis <David.Francis@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] We explicitly disable DFS bypass support when creating DC. Support for this feature should now be in place so it can be left implicitly enabled. [How] Remove the line that disables DFS bypass support. Note: This option was actually reset to false anyway for most of the hardware I've tested on making this particular line misleading in the first place. This patch also fixes this issue. Signed-off-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] While there is support for using and quering DFS bypass clocks the hardware is never notified to enter DFS bypass mode for dce110. [How] Add a flag that can be set when programming the display engine PLL to enable DFS bypass mode. If this flag is set then the hardware is notified to enter DFS bypass mode and the correct display engine clock frequency can be acquired. Signed-off-by:
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Tony Cheng authored
Signed-off-by:
Tony Cheng <tony.cheng@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Jun Lei authored
[why] Legacy IRI style is not linux friendly. [how] New function pointer call semantics will be used for all future PPLIB/DAL interfaces, and also some existing will be refactored. This change defines how the new function pointer structures will look, as well as implements Signed-off-by:
Jun Lei <Jun.Lei@amd.com> Reviewed-by:
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Charlene Liu authored
Signed-off-by:
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Rex Zhu authored
display can get clock info through this function. implement this function for vega10 and old asics. from vega12, there is no power state management, so need to add new interface to notify display the clock info Reviewed-by:
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Andrey Grodzovsky authored
It's useful to trace any dependency a job has on prevoius jobs. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
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Andrey Grodzovsky authored
During debug sessions I encountered a need to trace back a job dependecy a few steps back to the first failing job. This trace helpped me a lot. Signed-off-by:
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Nayan Deshmukh authored
This is the first attempt to move entities between schedulers to have dynamic load balancing. We just move entities with no jobs for now as moving the ones with jobs will lead to other compilcations like ensuring that the other scheduler does not remove a job from the current entity while we are moving. v2: remove unused variable and an unecessary check Signed-off-by:
Nayan Deshmukh <nayan26deshmukh@gmail.com> Reviewed-by:
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Nayan Deshmukh authored
The function selects the run queue from the rq_list with the least load. The load is decided by the number of jobs in a scheduler. v2: avoid using atomic read twice consecutively, instead store it locally Signed-off-by: -
Nayan Deshmukh authored
To keep track of the scheduler load. Signed-off-by:
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Nayan Deshmukh authored
These are the potential run queues on which the jobs from this entity can be scheduled. We will use this to do load balancing. Signed-off-by:
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Rex Zhu authored
so driver can powergate acp block after asic initialized to save power. Reviewed-by:
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Rex Zhu authored
Call smu to power gate/ungate acp instand of only powr down acp tiles in acp block. when smu power gate acp: smu will turn off clock, power down acp tiles,check and enter in ULV state. when smu ungate acp: smu will exit ulv, turn on clocks, power on acp tiles. Reviewed-by:
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Vijendar Mukunda authored
Removed condition checks to skip the power gating feature for stoney platform. Reviewed-by:
Vijendar Mukunda <vijendar.mukunda@amd.com> Signed-off-by:
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Rex Zhu authored
if board uses AZ rather than ACP, we power down acp through smu to save power. v2: handle S3/S4 and hw_fini (Alex) Reviewed-by:
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Rex Zhu authored
when ACP block not enabled, we power off acp block to save power. Reviewed-by:
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Rex Zhu authored
Used wrong pp interface, the original interface is exposed by dpm on SI and paritial CI. Pointed out by Francis David <david.francis@amd.com> v2: dal only need to set min_dcefclk and min_fclk to smu. so use display_clock_voltage_request interface, instand of update all display configuration. Acked-by: -
Andrey Grodzovsky authored
Problem: When executing echo 1 > /sys/class/drm/card0/device/remove kasan warning as bellow and page fault happen because adev->gart.pages already freed by the time amdgpu_gart_unbind is called. BUG: KASAN: user-memory-access in amdgpu_gart_unbind+0x98/0x180 [amdgpu] Write of size 8 at addr 0000000000003648 by task bash/1828 CPU: 2 PID: 1828 Comm: bash Tainted: G W O 4.18.0-rc1-dev+ #29 Hardware name: Gigabyte Technology Co., Ltd. AX370-Gaming/AX370-Gaming-CF, BIOS F3 06/19/2017 Call Trace: dump_stack+0x71/0xab kasan_report+0x109/0x390 amdgpu_gart_unbind+0x98/0x180 [amdgpu] ttm_tt_unbind+0x43/0x60 [ttm] ttm_bo_move_ttm+0x83/0x1c0 [ttm] ttm_bo_handle_move_mem+0xb97/0xd00 [ttm] ttm_bo_evict+0x273/0x530 [ttm] ttm_mem_evict_first+0x29c/0x360 [ttm] ttm_bo_force_list_clean+0xfc/0x210 [ttm] ttm_bo_clean_mm+0xe7/0x160 [ttm] amdgpu_ttm_fini+0xda/0x1d0 [amdgpu] amdgpu_bo_fini+0xf/0x60 [amdgpu] gmc_v8_0_sw_fini+0x36/0x70 [amdgpu] amdgpu_device_fini+0x2d0/0x7d0 [amdgpu] amdgpu_driver_unload_kms+0x6a/0xd0 [amdgpu] drm_dev_unregister+0x79/0x180 [drm] amdgpu_pci_remove+0x2a/0x60 [amdgpu] pci_device_remove+0x5b/0x100 device_release_driver_internal+0x236/0x360 pci_stop_bus_device+0xbf/0xf0 pci_stop_and_remove_bus_device_locked+0x16/0x30 remove_store+0xda/0xf0 kernfs_fop_write+0x186/0x220 __vfs_write+0xcc/0x330 vfs_write+0xe6/0x250 ksys_write+0xb1/0x140 do_syscall_64+0x77/0x1e0 entry_SYSCALL_64_after_hwframe+0x44/0xa9 RIP: 0033:0x7f66ebbb32c0 Fix: Split gmc_v{6,7,8,9}_0_gart_fini to postpone amdgpu_gart_fini to after memory managers are shut down since gart unbind happens as part of this procedure Signed-off-by:Junwei Zhang <Jerry.Zhang@amd.com> Acked-by:
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Emily Deng authored
SWDEV-146499: hang during multi vulkan process testing cause: the second frame's PREAMBLE_IB have clear-state and LOAD actions, those actions ruin the pipeline that is still doing process in the previous frame's work-load IB. fix: need insert pipeline sync if have context switch for SRIOV (because only SRIOV will report PREEMPTION flag to UMD) Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Reviewed-by:
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Christian König authored
At this point the command submission can still be interrupted. Signed-off-by:
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Christian König authored
We need to figure out the address after validating the BO, not before. Signed-off-by:
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