1. 24 Feb, 2022 7 commits
  2. 23 Feb, 2022 7 commits
  3. 16 Feb, 2022 2 commits
  4. 10 Feb, 2022 2 commits
    • Charles Keepax's avatar
      ASoC: wm_adsp: Correct control read size when parsing compressed buffer · a887f9c7
      Charles Keepax authored
      When parsing the compressed stream the whole buffer descriptor is
      now read in a single cs_dsp_coeff_read_ctrl; on older firmwares
      this descriptor is just 4 bytes but on more modern firmwares it is
      24 bytes. The current code reads the full 24 bytes regardless, this
      was working but reading junk for the last 20 bytes. However commit
      f444da38 ("firmware: cs_dsp: Add offset to cs_dsp read/write")
      added a size check into cs_dsp_coeff_read_ctrl, causing the older
      firmwares to now return an error.
      
      Update the code to only read the amount of data appropriate for
      the firmware loaded.
      
      Fixes: 04ae0859 ("ASoC: wm_adsp: Switch to using wm_coeff_read_ctrl for compressed buffers")
      Signed-off-by: default avatarCharles Keepax <ckeepax@opensource.cirrus.com>
      Link: https://lore.kernel.org/r/20220210172053.22782-1-ckeepax@opensource.cirrus.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      a887f9c7
    • Stephen Boyd's avatar
      ASoC: qcom: Actually clear DMA interrupt register for HDMI · c8d251f5
      Stephen Boyd authored
      In commit da0363f7 ("ASoC: qcom: Fix for DMA interrupt clear reg
      overwriting") we changed regmap_write() to regmap_update_bits() so that
      we can avoid overwriting bits that we didn't intend to modify.
      Unfortunately this change breaks the case where a register is writable
      but not readable, which is exactly how the HDMI irq clear register is
      designed (grep around LPASS_HDMITX_APP_IRQCLEAR_REG to see how it's
      write only). That's because regmap_update_bits() tries to read the
      register from the hardware and if it isn't readable it looks in the
      regmap cache to see what was written there last time to compare against
      what we want to write there. Eventually, we're unable to modify this
      register at all because the bits that we're trying to set are already
      set in the cache.
      
      This is doubly bad for the irq clear register because you have to write
      the bit to clear an interrupt. Given the irq is level triggered, we see
      an interrupt storm upon plugging in an HDMI cable and starting audio
      playback. The irq storm is so great that performance degrades
      significantly, leading to CPU soft lockups.
      
      Fix it by using regmap_write_bits() so that we really do write the bits
      in the clear register that we want to. This brings the number of irqs
      handled by lpass_dma_interrupt_handler() down from ~150k/sec to ~10/sec.
      
      Fixes: da0363f7 ("ASoC: qcom: Fix for DMA interrupt clear reg overwriting")
      Cc: Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
      Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
      Signed-off-by: default avatarStephen Boyd <swboyd@chromium.org>
      Link: https://lore.kernel.org/r/20220209232520.4017634-1-swboyd@chromium.orgSigned-off-by: default avatarMark Brown <broonie@kernel.org>
      c8d251f5
  5. 09 Feb, 2022 1 commit
  6. 08 Feb, 2022 5 commits
  7. 02 Feb, 2022 6 commits
  8. 31 Jan, 2022 1 commit
  9. 28 Jan, 2022 7 commits
  10. 26 Jan, 2022 2 commits